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Preliminary
Notice: This is not final specification.
Some parametric limits are subject to change.
DESCRIPTION
The M5M5T5672TG is a family of 18M bit synchronous SRAMs
organized as 262144-words by 72-bit. It is designed to eliminate
dead bus cycles when turning the bus around between reads
and writes, or writes and reads. Renesas's SRAMs are
fabricated with high performance, low power CMOS technology,
providing greater reliability. M5M5T5672TG operates on a single
2.5V power supply and are 2.5V CMOS compatible.
FEATURES
• Fully registered inputs and outputs for pipelined operation
• Fast clock speed: 200 MHz
• Fast access time: 3.2 ns
• Single 2.5V –5% and +5% power supply VDD
• Individual byte write (BWa# - BWh#) controls may be tied
LOW
• Single Read/Write control pin (W#)
• Snooze mode (ZZ) for power down
• Linear or Interleaved Burst Modes
• JTAG boundary scan support
APPLICATION
High-end networking products that require high bandwidth, such
as switches and routers.
Renesas LSIs
M5M5T5672TG – 20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
FUNCTION
Synchronous circuitry allows for precise cycle control triggered
by a positive edge clock transition.
Synchronous signals include : all Addresses, all Data Inputs,
all Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV),
Byte Write Enables (BWa#, BWb#, BWc#, BWd#, BWe#, BWf#,
BWg#, BWh#) and Read/Write (W#).
Write operations are controlled by the eight Byte Write
Enables (BWa# - BWh#) and Read/Write(W#) inputs. All writes
are conducted with on-chip synchronous self-timed write
circuitry.
Asynchronous inputs include Output Enable (G#), Clock (CLK)
and Snooze Enable (ZZ).
The HIGH input of ZZ pin puts the SRAM in the power-down
state.
The Linear Burst order (LBO#) is DC operated pin. LBO# pin
will allow the choice of either an interleaved burst, or a linear
burst.
All read, write and deselect cycles are initiated by the ADV
Low input. Subsequent burst address can be internally
generated as controlled by the ADV HIGH input.
PACKAGE
M5M5T5672TG
Bump
209(11X19) bump BGA
Body Size
14mm X 22mm
Bump Pitch
1mm
PART NAME TABLE
Part Name
M5M5T5672TG -20
Access
3.2ns
Cycle
5.0ns
Active Current
(max.)
450mA
Standby Current
(max.)
30mA
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Preliminary
M5M5T5672TG-20 REV.1.0

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BUMP LAYOUT(TOP VIEW)
209 bump BGA
Renesas LSIs
M5M5T5672TG – 20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
1 2 3 4 5 6 7 8 9 10 11
A DQg DQg A6 E2 A7 ADV A8 E3# A9 DQb DQb
B DQg DQg BWc# BWg# NC W# A17 BWb# BWf# DQb DQb
C DQg DQg BWh# BWd# NC E1# NC BWe# BWa# DQb DQb
D DQg DQg VSS NC NC G# NC NC VSS DQb DQb
E DQPg DQPc VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPf DQPb
F DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf
G DQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf
H DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf
J DQc DQc VDDQ VDDQ VDD MCH VDD VDDQ VDDQ DQf DQf
K NC NC CLK NC VSS CKE# VSS NC NC NC NC
L DQh DQh VDDQ VDDQ VDD MCH VDD VDDQ VDDQ DQa DQa
M DQh DQh VSS VSS VSS MCH VSS VSS VSS DQa DQa
N DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa
P
DQh DQh VSS
VSS VSS ZZ
VSS
VSS
VSS DQa DQa
R DQPd DQPh VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPa DQPe
T DQd DQd VSS NC NC LBO# NC NC VSS DQe DQe
U DQd DQd NC A3 NC A15 NC A11 NC DQe DQe
V DQd DQd A5
A4 A16 A1 A13 A12 A10 DQe DQe
W DQd DQd TMS TDI A2 A0 A14 TDO TCK
Note1. MCH means “Must Connect High”. MCH should be connected to HIGH.
DQe
DQe
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Preliminary
M5M5T5672TG-20 REV.1.0

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BLOCK DIAGRAM
Renesas LSIs
M5M5T5672TG – 20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
VDD
VDDQ
A0
A1
A2~17
18
ADDRESS
REGISTER
18 16
A1
D1
A0
D0
LINEAR/
INTERLEAVED
BURST
COUNTER
A1'
Q1
A0'
Q0
LBO#
CLK
CKE#
ZZ
ADV
BWa#
BWb#
BWc#
BWd#
BWe#
BWf#
BWg#
BWh#
W#
G#
E1#
E2
E3#
WRITE ADDRESS
REGISTER1
WRITE ADDRESS
REGISTER2
18
18
WRITE REGISTRY
AND
DATA COHERENCY
CONTROL LOGIC
READ
LOGIC
BYTE1
WRITE
DRIVERS
BYTE2
WRITE
DRIVERS
BYTE3
WRITE
DRIVERS
BYTE4
WRITE
DRIVERS
72
256Kx36
MEMORY
ARRAY
INPUT
REGISTER1
INPUT
REGISTER0
VSS
Note2. The BLOCK DIAGRAM does not include the Boundary Scan logic. See Boundary Scan chapter.
Note3. The BLOCK DIAGRAM illustrates simplified device operation. See TRUTH TABLE, PIN FUNCTION
and timing diagrams for detailed information.
DQa
DQPa
DQb
DQPb
DQc
DQPc
DQd
DQPd
DQe
DQPe
DQf
DQPf
DQg
DQPg
DQh
DQPh
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Preliminary
M5M5T5672TG-20 REV.1.0

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Renesas LSIs
M5M5T5672TG – 20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
PIN FUNCTION
Pin
A0~A17
BWa#, BWb#,
BWc#, BWd#,
Bwe#, BWf#,
BWg#, BWh#
CLK
E1#
E2
E3#
CKE#
G#
ADV
ZZ
Name
Synchronous
Address
Inputs
Synchronous
Byte Write
Enables
Clock Input
Synchronous
Chip Enable
Synchronous
Chip Enable
Synchronous
Chip Enable
Synchronous
Clock Enable
Output Enable
Synchronous
Address
Advance/Load
Snooze
Enable
W#
Synchronous
Read/Write
DQa,DQPa,DQb,DQPb,
DQc,DQPc,DQd,DQPd,
DQe,DQPe,DQf,DQPf,
DQg,DQPg,DQh,DQPh
Synchronous
Data I/O
LBO#
Burst Mode
Control
VDD
VSS
VDDQ
TDI
TDO
TCK
TMS
NC
VDD
VSS
VDDQ
Test Data Input
Test Data Output
Test Clock
Test Mode Select
No Connect
Function
These inputs are registered and must meet the setup and hold times around the rising edge of
CLK. A0 and A1 are the two least significant bits (LSB) of the address field and set the internal
burst counter if burst is desired.
These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and
must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be
asserted on the same cycle as the address. BWs are associated with addresses and apply to
subsequent data. BWa# controls DQa, DQPa pins; BWb# controls DQb, DQPb pins; BWc#
controls DQc, DQPc pins; BWd# controls DQd, DQPd pins; BWe# controls DQe, DQPe pins;
BWf# controls DQf, DQPf pins; BWg# controls DQg, DQPg pins; BWh# controls DQh, DQPh pins.
This signal registers the address, data, chip enables, byte write enables and burst control inputs
on its rising edge.
All synchronous inputs must meet setup and hold times around the clock's rising edge.
This active LOW input is used to enable the device and is sampled only when a new external
address is loaded (ADV is LOW).
This active HIGH input is used to enable the device and is sampled only when a new external
address is loaded (ADV is LOW). This input can be used for memory depth expansion.
This active LOW input is used to enable the device and is sampled only when a new external
address is loaded (ADV is LOW). This input can be used for memory depth expansion.
This active LOW input permits CLK to propagate throughout the device. When HIGH, the device
ignores the CLK input and effectively internally extends the previous CLK cycle. This input must
meet setup and hold times around the rising edge of CLK.
This active LOW asynchronous input enable the data I/O output drivers.
When HIGH, this input is used to advance the internal burst counter, controlling burst access after
the external address is loaded. When HIGH, W# is ignored. A LOW on this pin permits a new
address to be loaded at CLK rising edge.
This active HIGH asynchronous input causes the device to enter a low-power standby mode in
which all data in the memory array is retained. When active, all other inputs are ignored. When
this pin is LOW or NC, the SRAM normally operates.
This active input determines the cycle type when ADV is LOW. This is the only means for
determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice
versa) other than by loading a new address. A LOW on the pin permits BYTE WRITE operations
and must meet the setup and hold times around the rising edge of CLK. Full bus width WRITEs
occur if all byte write enables are LOW.
Byte “a” is DQa , DQPa pins; Byte “b” is DQb, DQPb pins; Byte “c” is DQc, DQPc pins; Byte “d” is
DQd,DQPd pins; Byte “e” is DQe, DQPe pins; Byte “f” is DQf, DQPf pins; Byte “g” is DQg, DQPg
pins; Byte “h” is DQh, DQPh pins. Input data must meet setup and hold times around CLK rising
edge.
This DC operated pin allows the choice of either an interleaved burst or a linear burst. If this pin is
HIGH or NC, an interleaved burst occurs. When this pin is LOW, a linear burst occurs, and input
leak current to this pin.
Core Power Supply
Ground
I/O buffer Power supply
These pins are used for Boundary Scan Test.
These pins are not internally connected and may be connected to ground.
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Preliminary
M5M5T5672TG-20 REV.1.0

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Renesas LSIs
M5M5T5672TG – 20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
DC OPERATED TRUTH TABLE
Name
Input Status
Operation
LBO#
HIGH or NC
LOW
Interleaved Burst Sequence
Linear Burst Sequence
Note4. LBO# is DC operated pin.
Note5. NC means No Connection.
Note6. See BURST SEQUENCE TABLE about interleaved and Linear Burst Sequence.
BURST SEQUENCE TABLE
(1) Interleaved Burst Sequence (when LBO# = HIGH or NC)
Operation
A17~A2
First access, latch external address
A17~A2
Second access(first burst address)
latched A17~A2
Third access(second burst address)
latched A17~A2
Fourth access(third burst address)
latched A17~A2
0,0
0,1
1,0
1,1
A1,A0
0,1 1,0
0,0 1,1
1,1 0,0
1,0 0,1
1,1
1,0
0,1
0,0
(2) Linear Burst Sequence (when LBO# = LOW)
Operation
A17~A2
First access, latch external address
A17~A2
Second access(first burst address)
latched A17~A2
Third access(second burst address)
latched A17~A2
Fourth access(third burst address)
latched A17~A2
Note7. The burst sequence wraps around to its initial state upon completion.
0,0
0,1
1,0
1,1
A1,A0
0,1 1,0
1,0 1,1
1,1 0,0
0,0 0,1
1,1
0,0
0,1
1,0
TRUTH TABLE
E1# E2 E3# ADV W# BWx# G# CKE# ZZ# CLK Address used
Operation
H X X L X X X L L L->H
None
Deselect Cycle
X L X L X X X L L L->H
None
Deselect Cycle
X X H L X X X L L L->H
None
Deselect Cycle
X X X H X X X L L L->H
None
Continue Deselect Cycle
L H L L H X L L L L->H
External
Read Cycle, Begin Burst
X X X H X X L L L L->H
Next Read Cycle, Continue Burst
L H L L H X H L L L->H
External
NOP/Dummy Read, Begin Burst
X X X H X X H L L L->H
Next Dummy Read, Continue Burst
L H L L L L X L L L->H
External
Write Cycle, Begin Burst
X X X H X L X L L L->H
Next Write Cycle, Continue Burst
L H L L L H X L L L->H
None
NOP/Write Abort, Begin Burst
X X X H X H X L L L->H
Next Write Abort, Continue Burst
X X X X X X X H L L->H
Current
Ignore Clock edge, Stall
XXX X X X X X H
X
None
Snooze Mode
Note8. “H” = input VIH; “L” = input VIL; “X” = input VIH or VIL.
Note9. BWx#=H means all Synchronous Byte Write Enables (BWa#,BWb#,BWc#,BWd#) are HIGH. BWx#=L means one or more
Synchronous Byte Write Enables are LOW.
Note10. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
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Preliminary
M5M5T5672TG-20 REV.1.0