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Preliminary Datasheet
M62353P/FP/GP
8-bit 8ch D/A Converter with Buffer Amplifiers
R03DS0042EJ0400
Rev.4.00
Jun 03, 2011
Description
The M62353 is an integrated circuit semiconductor of CMOS structure with 8 channels of built-in D/A converters with
output buffer operational amplifiers.
The 3-wire serial interface method is used for the transfer format of digital data to allow connection with
microcomputer with minimum wiring.
It is able to cascading serial use with DO terminal.
The output buffer operational amplifier operates in the whole voltage range from power supply to ground for both
input/output.
Features
12-bit serial data input (3-wire serial data transfer method)
Highly stable output buffer operational amplifier allow operation in the all voltage range from power supply to
ground.
Application
Adjustment/control of industrial or home-use electronic equipment, such as VTR camera, VTR set, TV, and CRT
display.
Block Diagram
GND
AO1
DI CLK LD DO
AO8
VCC
16 15 14 13 12 11 10 9
Ch1
8-bit R-2R
+ segment
D/A converter
8-bit
latch
....
(8)
12-bit shift register
D0 1 2 3 4 5 6 D7 D8 9 10 D11
(8)
(8)
Address
decoder
........
8
D/A
L
(8)
8-bit
latch
Ch2
8-bit R-2R
+ segment
D/A converter
L
3
D/A
L
4
D/A
L
5
D/A
L
6
D/A
L
7
D/A
Buffer
OP AMP
1 23 45 6
VSS
AO2
AO3
AO4
AO5
AO6
(VrefL)
78
AO7 VDD
(VrefU)
R03DS0042EJ0400 Rev.4.00
Jun 03, 2011
Page 1 of 9

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M62353P/FP/GP
Pin Arrangement
VSS
(VrefL)
AO2
AO3
AO4
AO5
AO6
AO7
VDD
(VrefU)
M62353P/FP/GP
1 16 GND
2 15 AO1
3 14 DI
4 13 CLK
5 12 LD
6 11 DO
7 10 AO8
8 9 VCC
(Top view)
Outline: PRDP0016AA-A (16P4) [P] (not recommend for new design)
PRSP0016DE-A (16P2N-A) [FP]
PLSP0016JA-A (16P2E-A) [GP]
Pin Description
Pin No.
14
11
13
12
15
2
3
4
5
6
7
10
9
16
8
1
Pin Name
Dl
DO
CLK
LD
AO1
AO2
AO3
AO4
AO5
AO6
AO7
AO8
VCC
GND
VDD
VSS
Function
Serial data input terminal
Serial data output terminal
Serial clock input terminal
LD terminal input high level then latch circuit data load
8-bit D/A converter output terminal
Power supply terminal
Digital and analog common GND
D/A converter upper reference voltage input terminal
D/A converter lower reference voltage input terminal
Preliminary
R03DS0042EJ0400 Rev.4.00
Jun 03, 2011
Page 2 of 9

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M62353P/FP/GP
Preliminary
Block Diagram for Explanation of Terminals
VCC
9
DI 14
CLK 13
12-bit shift register
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
GND
16
11 DO
(8)
D0 ..... D7
1 8-bit latch
8-bit R-2R
+ segment
D/A converter
A1
Address decoder
(8) 1 2 3 4 5 6 7 8
............................... 8
...............................
.........................................
D0 ..... D7
8-bit latch
8-bit R-2R
+ segment
D/A converter
A8
12 LD
8 15
VDD
AO1
(VrefU)
10 1
AO8
VSS
(VrefL)
Absolute Maximum Ratings
Item
Supply voltage
D/A converter upper reference voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Symbol
VCC
VDD
VIN
VO
Pd
Topr
Tstg
Ratings
–0.3 to +7.0
–0.3 to +7.0
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
450 (P) / 300 (FP) / 150 (GP)
–20 to +85
–40 to +125
Unit
V
V
V
V
mV
C
C
R03DS0042EJ0400 Rev.4.00
Jun 03, 2011
Page 3 of 9

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M62353P/FP/GP
Preliminary
Electrical Characteristics
Digital Part
(VCC, VrefU = +5 V 10%, VCC VrefU, GND, VrefL = 0 V, Ta = –20C to +85°C, unless otherwise noted.)
Limits
Item
Symbol Min
Typ
Max Unit
Test Conditions
Supply voltage
VCC
4.5 5.0
5.5 V
Circuit current
Input leak current
ICC
IILK
— 1.0
–10 —
2.5 mA CLK = 1 MHz operation
IOA = 0 A
10 A VIN = 0 to VCC
Input low voltage
VIL
0.2 VCC
V
Input high voltage
VIH
0.8 VCC
—V
Output low voltage
Output high voltage
VOL
VOH
VCC – 0.4
0.4 V IOL = 2.5 mA
— V IOH = –400 A
Analog Part
Item
Current dissipation
D/A converter upper
reference voltage range
D/A converter lower
reference voltage range
Buffer amplifier output
voltage range
Buffer amplifier output
drive range
Differential nonlinearity
error
Nonlinearity error
Zero code error
Full scale error
Output capacitive load
Buffer amplifier output
impedance
(VCC, VrefU = + 5 V 10%, VCC VrefU, Ta = –20C to +85°C, unless otherwise noted.)
Limits
Symbol Min Typ Max Unit
Test Conditions
IDD — 0.9 1.7 mA VrefU = 5 V, VrefL = 0 V
Data condition; at maximum current
VDD 3.5 — VCC V The output dose not necessarily be
the value within the reference voltage
VSS
GND
— VCC – 3.5 V setting range. The output value is
determined by the buffer amplifier
output voltage range (VAO)
VAO 0.1 — VCC – 0.1 V IOA = 100 A
0.2 — VCC – 0.2
IOA = 500 A
IAO
–1 —
1 mA Upper side saturation voltage = 0.3 V
Lower side saturation voltage = 0.2 V
SDL
–1.0 —
1.0 LSB VrefU = 4.79 V
VrefL = 0.95 V
SL
SZERO
–1.5
–2
1.5 LSB VCC = 5.5 V (15 mV/LSB)
2 LSB Without load (IAO = 0 A)
SFULL
–2
2 LSB
CO — — 0.1 F
RO — 5 —
R03DS0042EJ0400 Rev.4.00
Jun 03, 2011
Page 4 of 9

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M62353P/FP/GP
Preliminary
AC Characteristics
(VCC, VrefU = +5 V 10%, VCC VrefU, GND, VrefL = 0 V, Ta = –20 to +85C, unless otherwise noted.)
Limits
Item
Symbol Min Typ Max Unit
Test Conditions
Clock "L" pulse width
tCKL
200 —
— ns
Clock "H" pulse width
tCKH
200 —
— ns
Clock rise time
tCR — — 200 ns
Clock fall time
tCF — — 200 ns
Data setup time
tDCH 30 — — ns
Data hold time
tCHD 60 — — ns
LD setup time
tCHL
200 —
— ns
LD hold time
tLDC
100 —
— ns
LD "H" pulse width
Data output delay time
D/A output setting time
tLDH
tDO
tLDD
100 —
— ns
70 — 350 ns CL 100 pF
— — 300 s CL 100 pF VAO: 0.5 4.5 V
The time until the output becomes
the final value of 1/2 LSB
Timing Chart
tCR
tCKH
tCF
CLK
DI
LD
tCKL
tDCH
tCHD
tCHL
tLDH
tLDC
D/A
output
DO
output
tLDD
tDO
R03DS0042EJ0400 Rev.4.00
Jun 03, 2011
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