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July 1999
COP8SE Family
8-Bit CMOS ROM Based and OTP Microcontrollers with
4k Memory and 128 Bytes EERAM
General Description
The COP8SEx5 Family ROM based microcontrollers are
highly integrated COP8Feature core devices with 4k
memory and advanced features including EERAM.
COP8SER7 devices are pin and software compatible (differ-
ent VCC range), 32k OTP (One Time Programmable) ver-
sions for engineering development use with a range of
COP8 software and hardware development tools.
Family features include an 8-bit memory mapped architec-
ture, 10 MHz CKI with 1µs instruction cycle, 128 bytes of EE-
RAM, one multi-function 16-bit timer/counter, idle timer with
MIWU, MICROWIRE/PLUS, serial I/O, crystal or R/C oscil-
lator, two power saving HALT/IDLE modes, Schmitt trigger
inputs, software selectable I/O options, WATCHDOGtimer
and Clock Monitor, Low EMI 2.7V to 5.5V operation, and
16/20 pin packages.
Devices included in this data sheet are:
Device
OSC Memory (bytes) RAM (bytes) EERAM I/O Pins Package
Temperature
COP8SEC5
4k ROM
128 128 bytes 12/16 16/20 SOIC -40 to +85˚C, -40 to +135˚C
COP8SER7-XE xtal 32k OTP EPROM 128 128 bytes 16 20 SOIC -40 to +85˚C, Engineering
COP8SER7-RE R/C 32k OTP EPROM 128 128 bytes 16 20 SOIC -use only
Key Features
n 256 bytes data memory
— 128 bytes RAM
— 128 bytes EERAM
n OTP with security feature (SER7)
n Quiet Design (low radiated emissions)
n Multi-Input Wakeup pins with optional interrupts (8 pins)
n User selectable clock options:
— R/C oscillator
— Crystal oscillator
Other Features
n Fully static CMOS, with low current drain
n Available with Crystal (-XE) or RC (-RE) oscillator
n Two power saving modes: HALT and IDLE
n 1 µs instruction cycle time
n 4k bytes on-board masked ROM or 32k bytes OTP
n Single supply operation: 2.7V — 5.5V
n MICROWIRE/PLUS Serial Peripheral Interface
Compatible
n Nine multi-source vectored interrupts servicing
— EERAM write complete
— External interrupt
— Idle Timer T0
— One Timer (with 2 Interrupts)
— MICROWIRE/PLUS Serial Interface
— Multi-Input Wake Up
— Software Trap
— Default VIS
n Idle Timer with programmable interrupt interval
n One 16 bit timer with two 16-bit registers supporting:
— Processor Independent PWM mode
— External Event counter mode
— Input Capture mode
n 8-bit Stack Pointer SP (stack in RAM)
n Two 8-bit Register Indirect Data Memory Pointers
n Versatile instruction set
n True bit manipulation
n Memory mapped I/O
n BCD arithmetic instructions
n WATCHDOG and Clock Monitor logic
n Software selectable I/O options:
— TRI-STATE® Output:
— Push-Pull Output
— Weak Pull Up Input
— High Impedance Input
n Schmitt trigger inputs on ports G and L
n Temperature ranges:
— −40˚C to +85˚C
— −40˚C to +135˚C (SEC5 only)
n Packaging: 16, and 20 SO (SEC5); 20 SO (SER7)
n Real time emulation and full program debug offered by
MetaLink Development System
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
MICROWIRE/PLUS, COP8, MICROWIREand WATCHDOGare trademarks of National Semiconductor Corporation.
iceMASTERis a trademark of MetaLink Corporation.
PC® is a registered trademark of International Business Machines Corporation.
© 1999 National Semiconductor Corporation DS100973
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Block Diagram
DS100973-44
FIGURE 1. Block Diagram
1.0 Device Description
1.1 ARCHITECTURE
The COP8 family is based on a modified Harvard architec-
ture, which allows data tables to be accessed directly from
program memory. This is very important with modern
microcontroller-based applications, since program memory
is usually ROM or EPROM, while data memory is usually
RAM. Consequently data tables need to be contained in
non-volatile memory, so they are not lost when the microcon-
troller is powered down. Non-memory for the storage of data
variables is provided by the EERAM in the COP8SEC5 and
COP8SER7. In a Harvard architecture, instruction fetch and
memory data transfers can be overlapped with a two stage
pipeline, which allows the next instruction to be fetched from
program memory while the current instruction is being ex-
ecuted using data memory. This is not possible with a Von
Neumann single-address bus architecture.
The COP8 family supports a software stack scheme that al-
lows the user to incorporate many subroutine calls. This ca-
pability is important when using High Level Languages. With
a hardware stack, the user is limited to a small fixed number
of stack levels.
1.2 INSTRUCTION SET
In today’s 8-bit microcontroller application arena cost/
performance, flexibility and time to market are several of the
key issues that system designers face in attempting to build
well-engineered products that compete in the marketplace.
Many of these issues can be addressed through the manner
in which a microcontroller’s instruction set handles process-
ing tasks. And that’s why the COP8 family offers a unique
and code-efficient instruction set — one that provides the
flexibility, functionality, reduced costs and faster time to mar-
ket that today’s microcontroller based products require.
Code efficiency is important because it enables designers to
pack more on-chip functionality into less program memory
space (ROM/OTP). Selecting a microcontroller with less pro-
gram memory size translates into lower system costs, and
the added security of knowing that more code can be packed
into the available program memory space.
1.2.1 Key Instruction Set Features
The COP8 family incorporates a unique combination of in-
struction set features, which provide designers with optimum
code efficiency and program memory utilization.
Single Byte/Single Cycle Code Execution
The efficiency is due to the fact that the majority of instruc-
tions are of the single byte variety, resulting in minimum pro-
gram space. Because compact code does not occupy a sub-
stantial amount of program memory space, designers can
integrate additional features and functionality into the micro-
controller program memory space. Also, the majority instruc-
tions executed by the device are single cycle, resulting in
minimum program execution time. In fact, 77% of the instruc-
tions are single byte single cycle, providing greater code and
I/O efficiency, and faster code execution.
1.2.2 Many Single-Byte, Multifunction Instructions
The COP8 instruction set utilizes many single-byte, multi-
function instructions. This enables a single instruction to ac-
complish multiple functions, such as DRSZ, DCOR, JID, LD
(Load) and X (Exchange) instructions with post-incrementing
and post-decrementing, to name just a few examples. In
many cases, the instruction set can simultaneously execute
as many as three functions with the same single-byte in-
struction.
JID: (Jump Indirect); Single byte instruction; decodes exter-
nal events and jumps to corresponding service routines
(analogous to “DO CASE” statements in higher level lan-
guages).
LAID: (Load Accumulator-Indirect); Single byte look up table
instruction provides efficient data path from the program
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1.0 Device Description (Continued)
memory to the CPU. This instruction can be used for table
lookup and to read the entire program memory for checksum
calculations.
RETSK: (Return Skip); Single byte instruction allows return
from subroutine and skips next instruction. Decision to
branch can be made in the subroutine itself, saving code.
AUTOINC/DEC: (Auto-Increment/Auto-Decrement); These
instructions use the two memory pointers B and X to effi-
ciently process a block of data (analogous to “FOR NEXT” in
higher level languages).
1.2.3 Bit-Level Control
Bit-level control over many of the microcontroller’s I/O ports
provides a flexible means to ease layout concerns and save
board space. All members of the COP8 family provide the
ability to set, reset and test any individual bit in the data
memory address space, including memory-mapped I/O ports
and associated registers.
Connection Diagrams
1.2.4 Register Set
Three memory-mapped pointers handle register indirect ad-
dressing and software stack pointer functions. The memory
data pointers allow the option of post-incrementing or post-
decrementing with the data movement instructions (LOAD/
EXCHANGE). And 15 memory-maped registers allow de-
signers to optimize the precise implementation of certain
specific instructions.
1.3 PACKAGING/PIN EFFICIENCY
Real estate and board configuration considerations demand
maximum space and pin efficiency, particularly given today’s
high integration and small product form factors. Microcontrol-
ler users try to avoid using large packages to get the I/O
needed. Large packages take valuable board space and in-
crease device cost, two trade-offs that microcontroller de-
signs can ill afford.
The COP8 family offers a wide range of packages and does
not waste pins: up to 90.9% (or 40 pins in the 44-pin pack-
age, these packages are not available on all COP8 devices)
are devoted to useful I/O.
DS100973-6
Top View
Order Number COP8SEC516M
See NS Package Number M16B
DS100973-43
Top View
Order Number COP8SEC520M or COP8SER720M
See NS Package Number M20B
FIGURE 2. Connection Diagrams
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Connection Diagrams (Continued)
Pinouts for 16-, and 20-Pin Packages
Port
Type
Alt. Fun
L0 I/O MIWU
L1 I/O MIWU
L2 I/O MIWU
L3 I/O MIWU
L4 I/O MIWU
L5 I/O MIWU
L6 I/O MIWU
L7 I/O MIWU
G0 I/O
INT
G1 I/O WDOUT*
G2 I/O T1B
G3 I/O T1A
G4 I/O
SO
G5 I/O
SK
G6 I
SI
G7 I CKO
D0 O
D1 O
D2 O
D3 O
F0 I/O
F1 I/O
F2 I/O
F3 I/O
VCC
GND
CKI I
RESET
I
* G1 operation as WDOUT is controlled by Mask Option.
2.1 Ordering Information
20-Pin SO
7
8
9
10
11
12
13
14
17
18
19
20
1
2
3
4
6
15
5
16
16-Pin SO
7
8
9
10
13
14
15
16
1
2
3
4
6
11
5
12
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FIGURE 3. Part Numbering Scheme
4
DS100973-8

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3.0 Electrical Characteristics
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
Voltage at Any Pin
Total Current into VCC
Pin (Source)
Total Current out of
GND Pin (Sink)
7V
−0.3V to VCC +0.3V
80 mA
100 mA
Storage Temperature
Range
−65˚C to +150˚C
ESD Protection Level
2 kV(Human Body Model)
ESD Protection Level
(CKI pin)
150 V(Machine Model)
Note 1: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
Note 2: The COP8SER7 is for Engineering Development purpose only and
is not recommended for production or pre-production use.
DC Electrical Characteristics
−40˚C TA +85˚C unless otherwise specified.
Parameter
Conditions
Operating Voltage
Power Supply Rise Time
Power Supply Ripple (Note 4)
Peak-to-Peak
Supply Current (Note 5)
CKI = 10 MHz
VCC = 5.5V, tC = 1 µs
(SEC5)
(SER7)(Note 13)
HALT Current (Note 6)
VCC = 5.5V, CKI = 0 MHz
(SEC5)
(SER7)
IDLE Current (Note 5)
CKI = 10 MHz
VCC = 5.5V, tC = 1 µs
(SEC5)
(SER7)
Input Levels (VIH, VIL)
RESET
Logic High
Logic Low
CKI, All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage
Input Pullup Current
G and L Port Input Hysteresis
VCC = 5.5V
VCC = 5.5V, VIN = 0V
VCC = 5.5V
VCC = 2.7V
Min Typ
Max
Units
2.7 5.5 V
10
50 x 106
ns
0.1 Vcc
V
6 mA
10 mA
8 20
22
µA
µA
1.5 mA
1.5 mA
0.8 Vcc
0.7 Vcc
−2
−40
0.25 Vcc
0.31 Vcc
0.2 Vcc
0.2 Vcc
+2
−250
V
V
V
V
µA
µA
V
V
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