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ACT7005/7006 Single Package Solution Dual Transceiver/ Protocol/ SubsystemMaker : Aeroflex Circuit Technology
Shortcut : 700 700-1 700-2 700-3 700-4 700-5 700-6 700-CF 700-CRF 700-FE 700-FE 700-FS 700-FS 700-HA 700-HA 700-HB 700-HB 700-HC 700-HC 700-HK 700-HK 700-HL 700-HL 700-HL 700-HL2 700-HNC 700-HNK 700-HP 700-HP 700-HR 700-HR 700-HX 700-HXM 700-K 700-P 700-PH 700-PK 700-SA 700-SA 700-SC 700-SC 700-SE 700-SE 700-SH 700-SH 700-SK 700-SK 7000 7001 7002 7003 7003 7005 7006 70066-0071 70066-0110 70066-0211 700S-CF 700S-P 700SCFM 700U |
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Product Information |
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ACT7005/7006 Single Package Solution Dual Transceiver, Protocol, Subsystem Features • Incorporates Transceivers, Protocol, and System Interface Components into a Single Hybrid Package • Functions as a Remote Terminal or Bus Controller • Interfaces to µP as a Simple Peripheral Unit CIRCUIT TECHNOLOGY www.aeroflex.com • +5V Operation • Provides 2k by 16 of Double Buffered RAM Storage for Transmit and Receive Subaddresses • Pin Programmable for 8-bit or 16-bit Microprocessors • Full Military (-55°C to +125°C) Temperature Range General Description The ACT7005/6 Series provides a complete one package interface between the MIL-STD-1553 bus and all microprocessor systems. The hybrid provides all data buffers and control registers to function as a Bus Controller or Remote Terminal. Control of the hybrid by the subsystem is through simple I/O port commands. Internal hybrid logic removes all critical timing imposed on a typical subsystem, thereby simplifying the implementation of this interface. INTERRUPTS/ CONTROL SIGNALS µP INTERFACE BUS "0" DUAL TX/RX 1553 PROTOCOL S U B S Y S T E M 8/16 BIT I/O RAM BUS "1" ACT7005 / ACT7006 Block Diagram eroflex Circuit Technology – Data Bus Modules For The Future © SCD7005 REV B 8/2/01 Aeroflex Circuit Technology 8 BIT INTERNAL HIGHWAY RT Command Word Register MUX ENCODER INTERFACE UNIT RECEIVE FIFO BUFFER TRANSMIT FIFO BUFFER Receive Command Register Command Word #1 Register 32 x 16 32 x 16 VW/CMD Word #2/AMD Register MUX DECODER "0" 1k x 16 Sync/Stat WD #2/RMD Register RECEIVE RAM Operation Register Driver Select and Enable DECODER "1" MUX 1k x 16 INPUT FIFO BUFFER OUTPUT FIFO BUFFER SELF TEST CIRCUITRY STATUS WORD CONTROL TRANSMIT RAM Status Word #1 Register INTERNAL HIGHWAY CONTROL ARBITRATION AND CONTROL LOGIC 32 x 16 32 x 16 BI-DIRECTIONAL I/O DATA BUFFER 8 or 16 BIT SYSTEMS BUS HANDSHAKE and CONTROL SIGNALS Control Signals and Interrupts ADDRESS DISCRETE INPUT/OUTPUT SIGNALS BUS "0" Transceiver "0" 2 BUS "1" Transceiver "1" Terminal Address Inputs SCD7005 REV B 8/2/01 Plainview NY (516) 694-6700 Figure 1 – FUNCTIONAL BLOCK DIAGRAM Parameter Power Supply Voltage (VCC) Power Supply Voltage (VCCL & VDD) Receiver Differential Input (DATA CH A/B / DATA CH A/B) Receiver Input Voltage (DATA CH A/B or DATA CH A/B – Common Mode) Operating Case Temperature Range (TC) Transmission Duty Cycle at T C = +125°C Min -0.3 -0.3 -10 -5 -55 - Max 7.0 7.0 +10 +5 +125 100 Units V V V V °C % Table 1 – Absolute Maximum Ratings Parameter/Condition Power Supply Voltage Total supply current "standby" mode or transmitting at less than 1% duty cycle (e.g. 20µs of transmission every 2ms or longer interval). 2/ Total supply current transmitting at 1MHz into a 35Ω load at Point A in Figure 1. 2/ 1/ Note: 1/ 2/ Symbol VCC ICC@1% Min 4.75 Typ 5 18 Max 5.5 30 Unit mA mA ICC @ 25% ICC @ 50% ICC @ 100% 150 300 600 175 350 700 mA mA mA Decreases linearly to applicable "standyby" values at zero duty cycle. Represents one channel only. Table 2 – Analog Transceiver Power Supply Characteristics Aeroflex Circuit Technology 3 SCD7005 REV B 8/2/01 Plainview NY (516) 694-6700 Parameter/Condition Differential impedance DC to 1MHz, See Figure 4 Differential voltage range Input common mode voltage range Common mode rejection ratio (from point A, Figure 4) Threshold characteristics (sine wave at 1MHz) NOTE: Threshold voltages refer Figure 4 Point A Point C Point A Point C Symbol ZIO Min 2K 1K Max Unit Ω Ω VDIR VICR CMRR VTH1 VTH2 -10 -5 40 0.8 0.56 +10 +5 VPEAK VPEAK dB 1.1 0.86 Vp-p Vp-p Table 3 – Analog Transceiver Electrical Characteristics (Receiver Section) (Over Full Temperature Range) Parameter / Condition Differential output level at point B, See Figure 4 140Ω Point B 70Ω Point C Differential Output Noise at Point A, See Figure 4 Output Offset at point A in Figure 4, 2.5µs after mid-bit crossing of parity bit of last word of a 660µs mes... |
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