Maker : Philips
Part No. : 74HC08

  Datasheet PDF : 74HC08.pdf
  Cross Reference : 74HC08 Cross Reference
  Buy Component : 74HC08 Find Stock and Price

Shortcut : 74HC00  74HC00  74HC00BQ  74HC00D  74HC00DB  74HC00N  74HC00PW  74HC01  74HC02  74HC02  74HC02AP  74HC03  74HC03  74HC04  74HC04  74HC04N  74HC05  74HC05  74HC05  74HC05  74HC05  74HC05  74HC07  74HC08  74HC08  74HC08  74HC09 

Product Information

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT08 Quad 2-input AND gate Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Quad 2-input AND gate FEATURES • Output capability: standard • ICC category: SSI GENERAL DESCRIPTION 74HC/HCT08 The 74HC/HCT08 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT08 provide the 2-input AND function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V ∑ (CL × VCC2 × fo) = sum of outputs 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC −1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. PARAMETER propagation delay nA, nB to nY input capacitance power dissipation capacitance per gate notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 7 3.5 10 11 3.5 20 HCT ns pF pF UNIT December 1990 2 Philips Semiconductors Product specification Quad 2-input AND gate PIN DESCRIPTION PIN NO. 1, 4, 9, 12 2, 5, 10, 13 3, 6, 8, 11 7 14 SYMBOL 1A to 4A 1B to 4B 1Y to 4Y GND VCC NAME AND FUNCTION data inputs data inputs data outputs ground (0 V) positive supply voltage 74HC/HCT08 Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. FUNCTION TABLE INPUTS nA Fig.5 HC logic diagram (one gate). Note 1. H = HIGH voltage level L = LOW voltage level L L H H nB L H L H OUTPUT nY L L L H Fig.6 Fig.4 Functional diagram. HCT logic diagram (one gate). December 1990 3 Philips Semiconductors Product specification Quad 2-input AND gate DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: SSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) 74HC SYMBOL PARAMETER +25 min. tPHL/ tPLH propagation delay nA, nB to nY output transition time typ. 25 9 7 19 7 6 max. 90 18 15 75 15 13 −40 to +85 min. max. 115 23 20 95 19 16 −40 to +125 min. max. 135 27 23 110 22 19 ns UNIT 74HC/HCT08 TEST CONDITIONS VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 Fig.7 tTHL/ tTLH ns Fig.7 December 1990 4 Philips Semiconductors Product specification Quad 2-input AND gate DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: SSI 74HC/HCT08 Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT nA, nB UNIT LOAD COEFFICIENT 0.6 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) 74HCT SYMBOL PARAMETER +25 min. tPHL/ tPLH tTHL/ tTLH propagation delay nA, nB to nY output transition time typ. 14 7 max. 24 15 −40 to +85 min. max. 30 19 −40 to +125 min. max. 36 22 ns ns 4.5 4.5 Fig.7 Fig.7 UNIT VCC (V) WAVEFORMS TEST CONDITIONS AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the input (nA, nB) to output (nY) propagation delays and the output transition times. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 5 ...

Link URL