Maker : Actel Corporation
Part No. : A1010B-xxxx

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Product Information

www.DataSheet4U.com ACT™ 1 Series FPGAs Features • 5V and 3.3V Families fully compatible with JEDEC specifications • Up to 2000 Gate Array Gates (6000 PLD equivalent gates) • Replaces up to 50 TTL Packages • Replaces up to twenty 20-Pin PAL® Packages • Design Library with over 250 Macro Functions • Gate Array Architecture Allows Completely Automatic Place and Route • Up to 547 Programmable Logic Modules • Up to 273 Flip-Flops • Data Rates to 75 MHz • Two In-Circuit Diagnostic Probe Pins Support Speed Analysis to 25 MHz • Built-In High Speed Clock Distribution Network • I/O Drive to 10 mA (5 V), 6 mA (3.3 V) • Nonvolatile, User Programmable • Fabricated in 1.0 micron CMOS technology Description A security fuse may be programmed to disable all further programming and to protect the design from being copied or reverse engineered. Product Family Profile Device Capacity Gate Array Equivalent Gates PLD Equivalent Gates TTL Equivalent Packages 20-Pin PAL Equivalent Packages Logic Modules Flip-Flops (maximum) Routing Resources Horizontal Tracks/Channel Vertical Tracks/Column PLICE Antifuse Elements User I/Os (maximum) Packages: A1010B A10V10B 1,200 3,000 30 12 295 147 22 13 112,000 57 44 PLCC 68 PLCC A1020B A10V20B 2,000 6,000 50 20 547 273 22 13 186,000 69 The ACT™ 1 Series of field programmable gate arrays (FPGAs) offers a variety of package, speed, and application combinations. Devices are implemented in silicon gate, 1-micron two-level metal CMOS, and they employ Actel’s PLICE® antifuse technology. The unique architecture offers gate array flexibility, high performance, and instant turnaround through user programming. Device utilization is typically 95 to 100 percent of available logic modules. ACT 1 devices also provide system designers with unique on-chip diagnostic probe capabilities, allowing convenient testing and debugging. Additional features include an on-chip clock driver with a hardwired distribution network. The network provides efficient clock distribution with minimum skew. 44 PLCC 68 PLCC 84 PLCC 100 PQFP 100 PQFP 80 VQFP 80 VQFP 84 CPGA 84 CPGA 84 CQFP 75 MHz 55 MHz 75 MHz 55 MHz Performance 5 V Data Rate (maximum) 3.3 V Data Rate (maximum) Note: See Product Plan on page 1-286 for package availability. The Designer and Designer Advantage™ Systems om .c 4U The user-definable I/Os are capable of driving at both TTL and CMOS drive levels. Available packages include plastic et chip carriers, ceramic and plastic quad e and ceramic J-leaded hand ceramic pin grid array. flatpacks, aS at .D w w w April 1996 The ACT 1 device family is supported by Actel’s Designer and Designer Advantage Systems, allowing logic design implementation with minimum effort. The systems offer Microsoft® Windows™ and X Windows™ graphical user interfaces and integrate with the resident CAE system to provide a complete gate array design environment: schematic capture, simulation, fully automatic place and route, timing verification, and device programming. The systems also include the ACTmap™ VHDL optimization and synthesis tool and the ACTgen™ Macro Builder, a powerful macro function generator for counters, adders, and other structural blocks. 1-283 © 1996 Actel Corporation www.DataSheet4U.com The systems are available for 386/486/Pentium™ PC and for HP™ and Sun™ workstations and for running Viewlogic®, Mentor Graphics®, Cadence™, OrCAD™, and Synopsys design environments. Figure 1 • Partial View of an ACT 1 Device ACT 1 Device Structure A partial view of an ACT 1 device (Figure 1) depicts four logic modules and distributed horizontal and vertical interconnect tracks. PLICE antifuses, located at intersections of the horizontal and vertical tracks, connect logic module inputs and outputs. During programming, these antifuses are addressed and programmed to make the connections required by the circuit application. The ACT 1 Logic Module The ACT 1 logic module is an 8-input...

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