Maker : AMIC Technology
Part No. : A63G7332

  Datasheet PDF : A63G7332.pdf
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Product Information

A63G7332 Series 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output Preliminary Document Title 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output Revision History Rev. No. 1.0 1.1 2.0 2.1 History Initial issue Change pin 14 description from VCC to NC Change package type from 100-pin TQFP to 100-pin LQFP Change fast access times from 4.5/5/5.5 ns to 4.2/4.5/5.0 ns Modify 100-pin LQFP symbol y dimensions Max. in mm : 0.08 → 0.1 Max. in inches : 0.003 → 0.004 Issue Date November, 1997 June 17, 1998 August 27, 1998 December 31, 1998 Remark Preliminary PRELIMINARY (December, 1998, Version 2.1) AMIC Technology, Inc. A63G7332 Series 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output Preliminary Features n n n n n n Fast access times: 4.2/4.5/5.0 ns (143/133/100 MHZ) Single +3.3V+10% or +3.3V-5% power supply Separate +2.5V+0.4V/-0.12V isolated output buffer 3.3V tolerant inputs Synchronous burst function Individual Byte Write control and Global Write n Registered output for pipelined applications n Three separate chip enables allow wide range of options for CE control, address pipelining n Selectable BURST mode n SLEEP mode (ZZ pin) provided n Available in 100-pin LQFP package General Description The A63G7332 is a high-speed, low-power SRAM containing 4,194,304 bits of bit synchronous memory, organized as 131,072 words by 32 bits. The A63G7332 combines advanced synchronous peripheral circuitry, 2-bit burst control, input registers, output registers and a 128K X 32 SRAM core to provide a wide range of data RAM applications. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. Synchronous inputs include all addresses (A0 A16), all data inputs (I/O1 - I/O32), active LOW chip enable ( CE ), two additional chip enables (CE2, CE2 ), burst control inputs ( ADSC , ADSP , ADV ), byte write enables ( BWE , BW1 , BW2 , BW3 , BW4 ) and Global Write ( GW ). Asynchronous inputs include output enable ( OE ), clock (CLK), BURST mode (MODE) and SLEEP mode (ZZ). Burst operations can be initiated with either the address status processor ( ADSP ) or address status controller ( ADSC ) input pin. Subsequent burst sequence burst addresses can be internally generated by the A63G7332 and controlled by the burst advance ( ADV ) pin. Write cycles are internally self-timed and synchronous with the rising edge of the clock (CLK). This feature simplifies the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/O1 - I/O8, BW2 controls I/O9 - I/O16, BW3 controls I/O17 - I/O24, and BW4 controls I/O25 - I/O32, all on the condition that BWE is LOW. GW LOW causes all bytes to be written. PRELIMINARY (December, 1998, Version 2.1) 1 AMIC Technology, Inc. A63G7332 Series Pin Configuration ADSC ADSP BWE GND BW4 BW3 BW2 BW1 VCC ADV CE2 CE2 CLK GW OE CE A6 A7 A8 82 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 NC I/O17 I/O18 VCCQ GNDQ I/O19 I/O20 I/O21 I/O22 GNDQ VCCQ I/O23 I/O24 NC VCC NC GND I/O25 I/O26 VCCQ GNDQ I/O27 I/O28 I/O29 I/O30 GNDQ VCCQ I/O31 I/O32 NC 100 81 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 NC I/O16 I/O15 VCCQ GNDQ I/O14 I/O13 I/O12 I/O11 GNDQ VCCQ I/O10 I/O9 GND NC VCC ZZ I/O8 I/O7 VCCQ GNDQ I/O6 I/O5 I/O4 I/O3 GNDQ VCCQ I/O2 I/O1 NC A63G7332 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 GND NC NC NC MODE NC A5 A4 A3 A2 A1 A0 A10 A11 A12 A13 A14 A15 VCC A16 PRELIMINARY (December, 1998, Version 2.1) 2 AMIC Technology, Inc. A63G7332 Series Block Diagram ZZ MODE MODE LOGIC ADV CLK CLK LOGIC ADSC ADSP BURST LOGIC ADDRESS COUNTER CLR A0-A16 ADDRESS REGISTERS 17 8 BYTE1 WRITE DRIVER BYTE2 WRITE DRIVER BYTE...

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