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Part No. : A63L73321E-12

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A63L73321 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output Preliminary Document Title 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Flowthrough Data Output Revision History Rev. No. 0.0 0.1 0.2 0.3 0.4 History Initial issue Change fast access times from 8.5/9.5/10 ns to 9.5/10/12 ns Change ICC1 from 300mA to 350mA(max.) Add description for 100/91/83 MHz Add description for 2E1D at page 1 Modify waveform at page 11 Delete -9.5 & -10 part number Change -12 cycle time from 12ns to 15ns Issue Date December 14, 1998 June 9, 1999 December 19, 1999 June 20, 2000 August 29, 2001 Remark Preliminary PRELIMINARY (August, 2000, Version 0.4) AMIC Technology, Inc. A63L73321 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output Preliminary Features n n n n n Fast access times: 12ns at 66MHz Single +3.3V+10% or +3.3V-5% power supply Synchronous burst function Individual Byte Write control and Global Write Double-cycle enable, single-cycle deselect n Three separate chip enables allow wide range of options for CE control, address pipelining n Selectable BURST mode n SLEEP mode (ZZ pin) provided n Available in 100-pin LQFP package General Description The A63L73321 is a high-speed, low-power SRAM containing 4,194,304 bits of bit synchronous memory, organized as 131,072 words by 32 bits. The A63L73321 combines advanced synchronous peripheral circuitry, 2-bit burst control, input registers, output buffer and a 128K X 32 SRAM core to provide a wide range of data RAM applications. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. Synchronous inputs include all addresses (A0 A16), all data inputs (I/O1 - I/O32), active LOW chip enable ( CE ), two additional chip enables (CE2, CE2 ), burst control inputs ( ADSC , ADSP , ADV ), byte write enables ( BWE , BW1 , BW2 , BW3 , BW4 ) and Global Write ( GW ). Asynchronous inputs include output enable ( OE ), clock (CLK), BURST mode (MODE) and SLEEP mode (ZZ). Burst operations can be initiated with either the address status processor ( ADSP ) or address status controller ( ADSC ) input pin. Subsequent burst sequence burst addresses can be internally generated by the A63L73321 and controlled by the burst advance ( ADV ) pin. Write cycles are internally self-timed and synchronous with the rising edge of the clock (CLK). This feature simplifies the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/O1 - I/O8, BW2 controls I/O9 - I/O16, BW3 controls I/O17 - I/O24, and BW4 controls I/O25 - I/O32, all on the condition that BWE is LOW. GW LOW causes all bytes to be written. PRELIMINARY (August, 2000, Version 0.4) 1 AMIC Technology, Inc. A63L73321 Pin Configuration ADSC ADSP BWE BW4 BW3 BW2 BW1 GND VCC ADV CLK CE2 CE2 GW OE CE A6 A7 A8 82 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 NC I/O17 I/O18 VCCQ GNDQ I/O19 I/O20 I/O21 I/O22 GNDQ VCCQ I/O23 I/O24 NC VCC NC GND I/O25 I/O26 VCCQ GNDQ I/O27 I/O28 I/O29 I/O30 GNDQ VCCQ I/O31 I/O32 NC 100 81 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 NC I/O16 I/O15 VCCQ GNDQ I/O14 I/O13 I/O12 I/O11 GNDQ VCCQ I/O10 I/O9 GND NC VCC ZZ I/O8 I/O7 VCCQ GNDQ I/O6 I/O5 I/O4 I/O3 GNDQ VCCQ I/O2 I/O1 NC A63L73321E 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VCC NC NC NC GND NC A10 A11 A12 A13 A14 A15 MODE A16 A5 A4 A3 A2 A1 A0 x PRELIMINARY (August, 2000, Version 0.4) 2 AMIC Technology, Inc. A63L73321 Block Diagram ZZ MODE MODE LOGIC ADV CLK CLK LOGIC ADSC ADSP BURST LOGIC ADDRESS COUNTER CLR A0-A16 ADDRESS REGISTERS 17 8 BYTE1 WRITE DRIVER 8 GW BWE BW1 BW2 BW3 BW4 BYTE WRITE ENABLE LOGIC 8 BYTE2 WRITE DRIVER BYTE3 WRITE DRIVER BYTE4 WRITE DRIVER ...

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