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Part No. : A63L73361

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A63L73361 128K X 36 Bit Synchronous High Speed SRAM with Preliminary Burst Counter and Flow-through Data Output Document Title 128K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flowthrough Data Output Revision History Rev. No. 0.0 History Initial issue Issue Date July 7, 2005 Remark Preliminary www.DataSheet4U.com PRELIMINARY (July, 2005, Version 0.0) AMIC Technology, Corp. A63L73361 128K X 36 Bit Synchronous High Speed SRAM with Preliminary Burst Counter and Flow-through Data Output Features Fast access times: 6.5/7.5/8.0 ns(153/133/117 MHz) Single 3.3V±5% power supply Synchronous burst function Individual Byte Write control and Global Write Three separate chip enables allow wide range of options for CE control, address pipelining Selectable BURST mode SLEEP mode (ZZ pin) provided Available in 100-pin LQFP package Industrial operating temperature range: -45°C to +125°C for -I series General Description The A63L73361 is a high-speed SRAM containing 4.5M bits of bit synchronous memory, organized as 128K words by 36 bits. The A63L73361 combines advanced synchronous peripheral circuitry, 2-bit burst control, input registers, output buffer and a 128K X 36 SRAM core to provide a wide range of data RAM applications. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. Synchronous inputs include all addresses (A0 A17), all data inputs (I/O1 - I/O36 ), active LOW chip enable ( CE ), two additional chip enables (CE2, CE2 ), burst control inputs ( ADSC , ADSP , ADV ), byte write enables ( BWE , BW1 , BW2 , BW3 , BW4 ) and Global Write ( GW ). Asynchronous inputs include output enable www.DataSheet4U.com ( OE ), clock (CLK), BURST mode (MODE) and SLEEP mode (ZZ). Burst operations can be initiated with either the address status processor ( ADSP ) or address status controller ( ADSC ) input pin. Subsequent burst sequence burst addresses can be internally generated by the A63L73361 and controlled by the burst advance ( ADV ) pin. Write cycles are internally self-timed and synchronous with the rising edge of the clock (CLK). This feature simplifies the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/O1 - I/O9, BW2 controls I/O10 - I/O18, BW3 controls I/O19 - I/O27, and BW4 controls I/O28 - I/O36, all on the condition that BWE is LOW. GW LOW causes all bytes to be written. PRELIMINARY (July, 2005, Version 0.0) 1 AMIC Technology, Corp. A63L73361 Pin Configuration ADSC GND VCC ADSP BWE BW4 BW3 BW2 BW1 CLK CE2 A6 A7 ADV CE2 GW OE CE A8 82 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 I/O19 I/O20 I/O21 VCCQ GNDQ I/O22 I/O23 I/O24 I/O25 GNDQ VCCQ I/O26 I/O27 NC VCC NC GND I/O28 I/O29 VCCQ GNDQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 81 A9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 I/O18 I/O17 I/O16 VCCQ GNDQ I/O15 I/O14 I/O13 I/O12 GNDQ VCCQ I/O11 I/O10 GND NC VCC ZZ I/O8 I/O7 VCCQ GNDQ I/O6 I/O5 I/O4 I/O3 GNDQ VCCQ I/O2 I/O1 I/O9 A63L73361E 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 www.DataSheet4U.com I/O30 I/O31 I/O32 I/O33 GNDQ VCCQ I/O34 I/O35 I/O36 NC A5 A4 A3 A2 A1 A0 GND NC MODE VCC NC A10 A11 A12 A13 A14 A15 PRELIMINARY (July, 2005, Version 0.0) 2 A16 NC AMIC Technology, Corp. A63L73361 Block Diagram ZZ MODE MODE LOGIC ADV CLK CLK LOGIC ADSC ADSP BURST LOGIC ADDRESS COUNTER CLR A0-A16 ADDRESS REGISTERS 17 9 BYTE1 WRITE DRIVER 9 GW BWE BW1 BYTE WRITE ENABLE LOGIC 9 BYTE2 WRITE DRIVER BYTE3 WRITE DRIVER BYTE4 WRITE DRIVER 9 9 128KX9X4 36 MEMORY OUTPUT BUFFER ARRAY www.DataSheet4U.com BW2 BW3 BW4 9 9 9 36 4 DATA-IN REGISTERS 4 CHIP ENABLE LOGIC CE CE2 CE2 OE I/O1 - I/O36 OUTPUT ENABLE LOGIC PRELIMINARY (July, 2005, Version 0.0) 3 AMIC Technology, Corp. A63L73361 Pin Description Pin No. Symbol Desc...

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