Maker : AMIC Technology
Part No. : A64S16161

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Product Information

A64S16161 Preliminary Features ● Memory Cell : Dynamic memory( DRAM ) ● Refresh: Completely free ● Power Down: Control by CS2( No Data Retention ) ● Byte Control : Capable of single byte operation ● Power Consumption: 100μA( Standby Current ) ● Operating Temperature Range: -40’C~+85’C ● Composition:2,097,152 Word X 16 Bit ● Supply Power Voltage:2.70V to 3.30V ● Access Time: 70nS ● Access Time ( Page Access Read ): 30nS ● I/O Terminal :Input / Output Common 3-state output 2M X 16 Bit Low Voltage Super RAM 1 A B C D E F G H LB# 2 OE# 3 A0 4 A1 5 A2 6 CE2 DQ8 UB# A3 A4 CE1# DQ0 DQ9 DQ10 A5 A6 DQ1 DQ2 VSS DQ11 A17 A7 DQ3 VCC Pin Description Pin Name CS1# CS2 WE# OE# A0 to A20 IO0-7 IO8-15 LB# UB# VCC VSS Description Chip select 1 ( Low Active ) Chip select 2 ( High Active ) Write enable ( Low Active ) Output enable ( Low Active ) Address Input ( A0 to A2 : Page Address) Lower Byte Input / Output Upper Byte Input / Output Lower Byte Control ( Low Active ) Upper Byte Control ( Low Active ) Power Supply Ground ( 0V) VCC DQ12 NC A16 DQ4 VSS DQ14 DQ13 A14 A15 DQ5 DQ6 DQ15 A19 A12 A13 WE# DQ7 A18 A8 A9 A10 A11 A20 Description A64S16161 is a virtually static RAM, which uses DRAM type memory cells, but it has refresh transparency, so that you need not to imply refresh operation. Furthermore the interface is completely compatible to a low power Asynchronous type SRAM, you can operate as same as the Asynchronous SRAM. A64S16161 is a 2,097,152 Words X 16 bit asynchronous random access memory on a monolithic CMOS chip with marvelous low power consumption technology. Its low power and also low noise makes it ideal for mobile applications. PRELIMINARY (December, 2003, Version 0.0) 1 AMIC Technology Corp. A64S16161 Block Diagram A0 A1 A2 A3 A4 A5 A6 Row Decoder A7 A8 Address Buffer A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 8 Column Decoder 256 Column Gate 256X16 13 8192 Memory Cell ATD Control 16 Refresh Control CS1# CS2 CS1#,CS2 Control Input / Output Buffer WE# OE# LB# UB# WE#,OE# LB#,UB# Control I / O0 ．．．．．．．．．．．．．． I / O15 PRELIMINARY (December, 2003, Version 0.0) 2 AMIC Technology Corp. A64S16161 Functions Truth Table A0-20 V V V V V V V V X X CS1# L L L L L L L L H X CS2 H H H H H H H H H L WE# H H H H H L L L X X OE# L L L X H H H H X X LB# L L H H X L L H X X UB# L H L H X L H L X X I/O0~7 Data-Out Data-Out High-Z High-Z High-Z Data-In Data-In High-Z High-Z High-Z I/O8~15 Data-Out High-Z Data-Out High-Z High-Z Data-In High-Z Data-In High-Z High-Z Mode Read Read Read Output Disable Output Disable Write Write Write Standby Power Down*¹ V : Valid Address. X : High or Low .*1 No Data Retention Read Operation It is possible to control data width by LB# and UB# pins. (1)Reading data from lower byte Date can be read when the address is set while holding CS1#=L, CS2=H, OE #=L , WE #= H and LB #=L. (2)Reading data from upper byte Date can be read when the address is set while holding CS1#=L, CS2=H, OE #=L , WE #= H and UB #=L. (3)Reading date from both bytes Date can be read when the address is set while holding CS1#=L, CS2=H, OE #=L , WE #= H , LB #=L and UB #=L. (4)Page access read Date can be read by changing A0-A2 when A3-A20 is set while holding CS1#=L, CS2=H, WE #=H, OE #=L, LB #=L and UB #=L. Writing Operation (1) Writing data into lower byte ( WE # control ) Data can be written by adding L pulse into WE # when the address is set while holding CS1#=L, CS2=H, OE #=H, LB #=L and UB #=H. The data on lower byte are latched up into the memory cell during WE # =L and LB # =L. (2) Writing data into lower byte (LB # control) Data can be written by adding L pulse into LB # when the address is set while holding CS1#=L, CS2 =H, OE#=H, UB# =H and WE#=L. The data on lower byte are latched up into the memory cell during WE# =L and LB# = L. (3) Writing data into upper byte (WE # control) Data can be written by adding L pulse int...

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