Maker : AMIC Technology
Part No. : A67P16181

  Datasheet PDF : A67P16181.pdf
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www.DataSheet4U.com A67P16181/A67P06361 Series Preliminary Document Title 2M X 18, 1M X 36 LVTTL, Flow-through ZeBLTM SRAM Revision History Rev. No. 0.0 0.1 2M X 18, 1M X 36 LVTTL, Flow-through ZeBLTM SRAM History Initial issue Error Correction: delete BWE pin in block diagram Issue Date March 25, 2004 August 6, 2004 Remark Preliminary PRELIMINARY (August, 2004, Version 0.1) AMIC Technology, Corp. A67P16181/A67P06361 Series Preliminary Features Fast access time: 6.5/7.5/8.5 ns (153, 133, 117 MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +2.5V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled and registered address, data and control signals Registered output for pipelined applications Three separate chip enables allow wide range of options for CE control, address pipelining Internally self-timed write cycle Selectable BURST mode (Linear or Interleaved) SLEEP mode (ZZ pin) provided Available in 100 pin LQFP package 2M X 18, 1M X 36 LVTTL, Flow-through ZeBLTM SRAM General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67P16181, A67P06361 SRAMs integrate a 2M X 18, 1M X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. The synchronous inputs include all address, all data inputs, active low chip enable ( CE ), two additional chip enables for easy depth expansion (CE2, CE2 ), cycle start input (ADV/ LD ), synchronous clock enable ( CEN ), byte write enables ( BW1 , BW2 , BW3 , BW4 ) and read/write (R/ W ). Asynchronous inputs include the output enable ( OE ), clock (CLK), SLEEP mode (ZZ, tied LOW if unused) and burst mode (MODE). Burst Mode can provide either interleaved or linear operation, burst operation can be initiated by synchronous address Advance/Load (ADV/ LD ) pin in Low state. Subsequent burst address can be internally generated by the chip and controlled by the same input pin ADV/ LD in High state. Write cycles are internally self-time and synchronous with the rising edge of the clock input and when R/ W is Low. The feature simplified the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/Oa pins; BW2 controls I/Ob pins; BW3 controls I/Oc pins; and BW4 controls I/Od pins. Cycle types can only be defined when an address is loaded. The SRAM operates from a +2.5V power supply, and all inputs and outputs are LVTTL-compatible. The device is ideally suited for high bandwidth utilization systems. PRELIMINARY (August, 2004, Version 0.1) 2 AMIC Technology, Corp. A67P16181/A67P06361 Series Pin Configuration OE ADV/ LD BW4 BW3 BW2 BW1 VCC CEN A18 CLK VSS CE2 CE2 CE R/W A6 A7 A17 1M X 36 2M X 18 A6 A7 A8 A8 82 CEN OE ADV/ LD BW2 BW1 VCC VSS CLK R/W A19 CE2 CE2 NC NC CE A18 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 100 81 80 79 78 77 76 75 74 73 72 71 70 69 68 I/Oc8 I/Oc0 I/Oc1 VCCQ VSSQ I/Oc2 I/Oc3 I/Oc4 I/Oc5 VSSQ VCCQ I/Oc6 I/Oc 7 VSS VCC VCC VSS I/Od 0 I/Od 1 VCCQ VSSQ I/Od 2 I/Od 3 I/Od 4 I/Od 5 VSSQ VCCQ I/Od6 I/Od7 I/Od8 NC NC NC VCCQ VSSQ NC NC I/Ob8 I/Ob7 VSSQ VCCQ I/Ob6 I/Ob5 VSS VCC VCC VSS I/Ob4 I/Ob3 VCCQ VSSQ I/Ob 2 I/Ob 1 I/Ob 0 NC VSSQ VCCQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A9 A9 A10 NC NC VCCQ VSSQ NC I/Oa0 I/Oa1 I/Oa2 VSSQ VCCQ I/Oa3 I/Oa4 VSS VSS VCC ZZ I/Oa5 I/Oa6 VCCQ VSSQ I/Oa7 I/Oa8 NC NC VSSQ VCCQ NC NC NC I/Ob8 I/Ob7 I/Ob6 VCCQ VSSQ I/Ob5 I/Ob4 I/Ob3 I/Ob2 VSSQ VCCQ I/Ob1 ...

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