Maker : Allegro MicroSystems
Part No. : A6B595KA

  Datasheet PDF : A6B595KA.pdf
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Shortcut : A6B595KA  A6B595KLW 

Product Information

6B595 ADVANCE INFORMATION (Subject to change without notice) January 24, 2000 NO CONNECTION LOGIC SUPPLY SERIAL DATA IN OUT 0 OUT 1 OUT 2 OUT 3 REGISTER CLEAR OUTPUT ENABLE GROUND NO CONNECTION GROUND SERIAL DATA OUT OUT 7 OUT 6 OUT 5 OUT 4 CLOCK STROBE GROUND 8-BIT SERIAL-INPUT, DMOS POWER DRIVER The A6B595KA and A6B595KLW combine an 8-bit CMOS shift register and accompanying data latches, control circuitry, and DMOS power driver outputs. Power driver applications include relays, solenoids, and other medium-current or high-voltage peripheral power loads. The serial-data input, CMOS shift register and latches allow direct interfacing with microprocessor-based systems. Serial-data input rates are over 5 MHz. Use with TTL may require appropriate pull-up resistors to ensure an input logic high. A CMOS serial-data output enables cascade connections in applications requiring additional drive lines. Similar devices with reduced rDS(on) are available as the A6595KA and A6595KLW. The A6B595 DMOS open-drain outputs are capable of sinking up to 500 mA. All of the output drivers are disabled (the DMOS sink drivers turned off) by the OUTPUT ENABLE input high. The A6B595KA is furnished in a 20-pin dual in-line plastic package. The A6B595KLW is furnished in a wide-body, small-outline plastic package (SOIC) with gull-wing leads. Copper lead frames, reduced supply current requirements, and low on-state resistance allow both devices to sink 150 mA from all outputs continuously, to ambient temperatures over 85°C. Data Sheet 26185.122 1 2 3 4 NC VDD NC 20 19 18 17 REGISTER REGISTER LATCHES LATCHES 5 6 7 8 9 10 CLR OE 16 15 14 CLK ST 13 12 11 Dwg. PP-029-12 Note that the A6B595KA (DIP) and the A6B595KLW (SOIC) are electrically identical and share a common terminal number assignment. ABSOLUTE MAXIMUM RATINGS at TA = 25°C Output Voltage, VO ............................... 50 V Output Drain Current, Continuous, IO .......................... 150 mA* Peak, IOM ................................... 500 mA† Single-Pulse Avalanche Energy, EAS ................................................. 30 mJ Logic Supply Voltage, VDD .................. 7.0 V Input Voltage Range, VI ................................... -0.3 V to +7.0 V Package Power Dissipation, PD ........................................... See Graph Operating Temperature Range, TA ................................. -40°C to +125°C Storage Temperature Range, TS ................................. -55°C to +150°C * Each output, all outputs on. † Pulse duration ≤ 100 µs, duty cycle ≤ 2%. Caution: These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high static electrical charges. FEATURES s 50 V Minimum Output Clamp Voltage s 150 mA Output Current (all outputs simultaneously) s 5 Ω Typical rDS(on) s Low Power Consumption s Replacements for TPIC6B595N and TPIC6B595DW Always order by complete part number: Part Number Package A6B595KA 20-pin DIP A6B595KLW 20-lead SOIC RθJA 55°C/W 70°C/W RθJC 25°C/W 17°C/W 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS 2.5 9 12 LOGIC SYMBOL G3 C2 R SRG8 C1 1D 2 4 5 6 A 2.0 SU FF IX 8 13 1.5 SU FF IX 'A ', R θJ A = 3 'LW ', R 55 °C /W 1.0 θJ =7 0° C/ W 7 14 0.5 15 16 0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150 2 17 18 Dwg. GS-004A Dwg. FP-043 FUNCTIONAL BLOCK DIAGRAM REGISTER CLEAR (ACTIVE LOW) CLOCK SERIAL DATA IN STROBE OUTPUT ENABLE (ACTIVE LOW) V DD LOGIC SUPPLY SERIAL DATA OUT SERIAL-PARALLEL SHIFT REGISTER D-TYPE LATCHES GROUND GROUND OUT 0 OUT N Dwg. FP-013-4 Grounds (terminals 10, 11, and 19) must be connected together externally. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1999, Allegro MicroSystems, Inc. 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER V IN DD OUT Dwg. EP-063 Dwg. EP-010-16 LOGIC INPUTS DMOS POWER DRIVER OU...

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