Maker : Analog Devices
Part No. : AD6649

  Datasheet PDF : AD6649.pdf
  Cross Reference : AD6649 Cross Reference
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Product Information

www.DataSheet4U.net IF Diversity Receiver AD6649 FEATURES SNR = 73.0 dBFS in a 95 MHz bandwidth at 185 MHz AIN and 245.76 MSPS SFDR = 85 dBc at 185 MHz AIN and 250 MSPS Noise density = −151.2 dBFS/Hz input at 185 MHz, −1 dBFS AIN and 250 MSPS Total power consumption: 1 W with fixed-frequency NCO, 95 MHz FIR filter 1.8 V supply voltages LVDS (ANSI-644 levels) outputs Integer 1-to-8 input clock divider (625 MHz maximum input) Integrated dual-channel ADC Sample rates of up to 250 MSPS IF sampling frequencies to 400 MHz Internal ADC voltage reference Flexible input range 1.4 V p-p to 2.1 V p-p (1.75 V p-p nominal) ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Integrated wideband digital processor 32-bit complex numerically controlled oscillator (NCO) FIR filter with 2 modes Real output from an fS/4 output NCO Amplitude detect bits for efficient AGC implementation Energy saving power-down modes Decimated, interleaved real LVDS data outputs AVDD FDA APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE General-purpose software radios Broadband data applications GENERAL DESCRIPTION The AD6649 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 14-bit, 250 MSPS ADCs and a wideband digital downconverter (DDC). The AD6649 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. FUNCTIONAL BLOCK DIAGRAM DRVDD THRESHOLD DETECT I DDR LVDS OUTPUT BUFFER SELECTABLE FIR FILTER AD6649 OR+ OR– D13+/D13– D0+/D0– VIN+A ADC VIN–A Q DC CORRECTION REFERENCE 32-BIT TUNING NCO SELECTABLE FIR FILTER DIGITAL INTERLEAVING fS/4 NCO Q DIVIDE 1 TO 8 DUTY CYCLE STABILIZER DCO GENERATION MULTICHIP SYNC PROGRAMMING DATA CLK+ CLK– DCO+ DCO– SYNC DC CORRECTION VIN–B ADC VIN+B SELECTABLE FIR FILTER I THRESHOLD DETECT SELECTABLE FIR FILTER SPI 09635-001 AGND FDB PDWN OEB SDIO SCLK CSB Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. AD6649 TABLE OF CONTENTS Features .............................................................................................. 1  Applications....................................................................................... 1  General Description ......................................................................... 1  Functional Block Diagram .............................................................. 1  Revision History ............................................................................... 2  Product Highlights ........................................................................... 3  Specifications..................................................................................... 4  ADC DC Specifications................................................................. 4  ADC AC Specifications .................................................

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