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Quad IF ReceiverMaker : Analog Devices Datasheet PDF : AD6657.pdf |
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Product Information |
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Quad IF Receiver AD6657 FEATURES 11-bit, 200 MSPS output data rate per channel Integrated noise shaping requantizer (NSR) Performance with NSR enabled SNR: 75.5 dBFS in 40 MHz band to 70 MHz @ 185 MSPS SNR: 73.7 dBFS in 60 MHz band to 70 MHz @ 185 MSPS Performance with NSR disabled SNR: 66.5 dBFS to 70 MHz @ 185 MSPS SFDR: 83 dBc to 70 MHz @ 185 MSPS Low power: 1.2 W @ 185 MSPS 1.8 V analog supply operation 1.8 V LVDS (ANSI-644 levels) output 1-to-8 integer clock divider Internal ADC voltage reference 1.75 V p-p analog input range (programmable to 2.0 V p-p) Differential analog inputs with 800 MHz bandwidth 95 dB channel isolation/crosstalk Serial port control User-configurable built-in self-test (BIST) capability Energy-saving power-down modes FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD DRGND AD6657 VIN+A VIN–A VCMA VIN+B VIN–B VCMB VIN+C VIN–C VCMC VIN+D VIN–D VCMD REFERENCE CLOCK DIVIDER SERIAL PORT SYNC PDWN 08557-001 PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 DC0±AB D0±AB DATA MULTIPLEXER AND LVDS DRIVERS PORT A D10±AB PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 DC0±CD D0±CD PORT B PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 D10±CD MODE SCLK SDIO CSB CLK+ CLK– APPLICATIONS Communications Diversity radio and smart antenna (MIMO) systems Multimode digital receivers (3G) WCDMA, LTE, CDMA2000 WiMAX, TD-SCDMA I/Q demodulation systems General-purpose www.DataSheet4U.com software radios Figure 1. PRODUCT HIGHLIGHTS 1. 2. Four ADCs are contained in a small, space-saving, 10 mm × 10 mm × 1.4 mm, 144-ball CSP_BGA package. Pin selectable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of up to 60 MHz at 185 MSPS. LVDS digital output interface configured for low cost FPGA families. 230 mW per ADC core power consumption. Operation from a single 1.8 V supply. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary or twos complement), NSR, power-down, test modes, and voltage reference mode. On-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems. 3. 4. 5. 6. 7. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. AD6657 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications.......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications ...... |
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