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Dual IF ReceiverMaker : Analog Devices Datasheet PDF : AD6659.pdf |
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Product Information |
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www.DataSheet4U.com Dual IF Receiver AD6659 FEATURES 12-bit, 80 MSPS output data rate per channel 1.8 V analog supply operation (AVDD) 1.8 V to 3.3 V output supply (DRVDD) Integrated noise shaping requantizer (NSR) Integrated quadrature error correction (QEC) Performance with NSR enabled SNR = 81 dBFS in 16 MHz band up to 30 MHz at 80 MSPS Performance with NSR disabled SNR = 72 dBFS up to 70 MHz at 80 MSPS SFDR = 90 dBc up to 70 MHz input at 80 MSPS Low power: 98 mW per channel at 80 MSPS Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input Serial port control options Offset binary, gray code, or twos complement data format Optional clock duty cycle stabilizer Integer 1-to-6 input clock divider Data output multiplex option Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out with programmable clock and data alignment FUNCTIONAL BLOCK DIAGRAM AVDD AGND SDIO SCLK SPI PROGRAMMING DATA CSB CMOS OUTPUT BUFFER ORA D11A (MSB) D0A (LSB) DCOA VIN+A VIN–A ADC 16 QUADRATURE ERROR AND DC OFFSET CORRECTION 12 NOISE SHAPING REQUANTIZER VREF SENSE VCM RBIAS REF SELECT MUX OPTION AD6659 DRVDD CMOS OUTPUT BUFFER ORB D11B (MSB) D0B (LSB) DCOB VIN+B VIN–B ADC 16 QUADRATURE ERROR AND DC OFFSET CORRECTION 12 NOISE SHAPING REQUANTIZER DIVIDE 1 TO 6 DUTY CYCLE STABILIZER MODE CONTROLS 08701-001 CLK+ CLK– SYNC DCS PDWN DFS OEB Figure 1. PRODUCT HIGHLIGHTS 1. The AD6659 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. SPI-selectable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of up to 70 MHz at 80 MSPS. SPI-selectable dc correction and quadrature error correction (QEC) that corrects for dc offset, gain, and phase mismatches between the two channels. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/data timing, offset adjustments, and voltage reference modes. The AD6659 is packaged in a 64-lead RoHS-compliant LFCSP that is pin compatible with the AD9269 16-bit ADC, the AD9268 16-bit ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC, the AD9231 12-bit ADC, and the AD9204 10-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS. APPLICATIONS Communications Diversity radio systems Multimode digital receivers 3G, W-CDMA, LTE, CDMA2000, TD-SCDMA, MC-GSM I/Q demodulation systems Smart antenna systems Battery-powered instruments General-purpose software radios 2. 3. 4. 5. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. AD6659 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 General Description ..................................... |
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