Maker : ETC
Part No. : AS7C256-15JC

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Product Information

High Performance 32K×8 CMOS SRAM 32K×8 CMOS SRAM (Common I/O) FEATURES • Organization: 32,768 words × 8 bits • High speed – 10/12/15/20/25/35 ns address access time – 3/3/4/5/6/8 ns output enable access time • Low power consumption – Active: – Standby: 660 mW max (10 ns cycle) 11 mW max, CMOS I/O 2.75 mW max, CMOS I/O, L version • Equal access and cycle times AS7C256 AS7C256L • Easy memory expansion with CE and OE inputs • TTL-compatible, three-state I/O • 28-pin JEDEC standard packages – 300 mil PDIP and SOJ Socket compatible with 7C512 and 7C1024 – 330 mil SOIC – 8×13.4 TSOP • ESD protection > 2000 volts • Latch-up current > 200 mA – Very low DC component in active power • 2.0V data retention (L version) LOGIC BLOCK DIAGRAM PIN ARRANGEMENT DIP, SOJ, SOIC Vcc GND INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A14 ROW DECODER I/O7 256×128×8 ARRAY (262,144) SENSE AMP A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 I/O0 COLUMN DECODER WE CONTROL CIRCUIT OE CE TSOP 8×13.4 A A A A A A A 7 8 9 10 11 12 13 AS7C256-01 SELECTION GUIDE 7C256-10 Maximum Address Access Time Maximum Output Enable Access Time Maximum Operating Current Maximum CMOS Standby Current 10 3 120 2.0 L 0.5 7C256-12 12 3 115 2.0 0.5 OE A11 A9 A8 A13 WE Vcc A14 A12 A7 A6 A5 A4 A3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 AS7C256 AS7C256 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 AS7C256-02 A1 A2 7C256-15 15 4 110 2.0 0.5 7C256-20 20 5 100 2.0 0.5 7C256-25 25 6 90 2.0 0.5 7C256-35 35 8 80 2.0 0.5 Unit ns ns mA mA mA ALLIANCE SEMICONDUCTOR AS7C256 AS7C256L FUNCTIONAL DESCRIPTION The AS7C256 is a high performance CMOS 262,144-bit Static Random Access Memory (SRAM) organized as 32,768 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20/25/35 ns with output enable access times (tOE) of 3/3/4/5/6/8 ns are ideal for high performance applications. A chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. When CE is HIGH the device enters standby mode. The standard AS7C256 is guaranteed not to exceed 11 mW power consumption in standby mode; the L version is guaranteed not to exceed 2.75 mW, and typically requires only 500 µW. The L version also offers 2.0V data retention, with maximum power consumption in this mode of 300 µW. A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) HIGH. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is HIGH, or write enable is LOW, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply. The AS7C256 is packaged in all high volume industry standard packages. ABSOLUTE MAXIMUM RATINGS Parameter Voltage on Any Pin Relative to GND Power Dissipation Storage Temperature (Plastic) Temperature Under Bias DC Output Current Symbol Vt PD Tstg Tbias Iout Min –0.5 – –55 –10 – Max +7.0 1.0 +150 +85 20 Unit V W oC oC mA NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificat...

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