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Search -----> MSC1162AMaker : Oki
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E2C0034-27-Y5 www.DataSheet4U.com ¡ Semiconductor MSC1162A ¡ Semiconductor 40-Bit Vacuum Fluorescent Display Tube Grid/Anode Driver This version: Nov. 1997 MSC1162A Previous version: Jul. 1996 GENERAL DESCRIPTION The MSC1162A is a monolithic IC designed for directly driving the grid and anode of the vacuum fluorescent display tube. The device contains a 40-bit bidirectional shift register, a 40-bit latch circuit, and 40-output circuit on a single chip. Display data is serially stored in the shift register at the rising edge of a clock pulse. Setting the CL pin low allows all the driver outputs to be driven low, which makes it possible to set the display blanking. Also, setting both of the CL and CHG pins high allows all the driver outputs to be driven high, which provides the easy testing of all lights after final assembly of a VFD tube panel. The MSC1162A is compatible with the MSC1162. FEATURES • Logic Supply Voltage (VCC) : 5V • Driver Supply Voltage (VHV): 65V • Driver Output Current IOHVH1 (Only one driver output : "H") : –40mA IOHVH2 (All the driver outputs : "H") : –2mA IOHVL:1mA • Directly connected to VFD tube without pull-down resistors • Data Transfer Speed: 4MHz • Package : 60-pin plastic SSOP (SSOP60-P-700-0.65-BK) (Product name : MSC1162AGS-BK) 1/14 www.DataSheet4U.com ¡ Semiconductor MSC1162A BLOCK DIAGRAM V HV V CC V CC CL CHG LS DIN CLK C SI HVO1 PO1 I-1 O-1 HVO2 PO2 40-Bit Bidirectional Shift Register I-2 O-2 40-Bit Latch HVO40 PO40 GND1 GND2 SO DOUT I-40 O-40 2/14 www.DataSheet4U.com ¡ Semiconductor MSC1162A INPUT AND OUTPUT CONFIGURATION Schematic Diagrams of Logic portion Input/Output Circuits and Driver Output Circuits Input Pin VCC VCC INPUT GND1 GND2 Output Pin VCC VCC DOUT GND2 GND1 3/14 www.DataSheet4U.com ¡ Semiconductor Driver Output Circuit MSC1162A VHV VHV Output GND 1 GND 1 4/14 www.DataSheet4U.com ¡ Semiconductor PIN CONFIGURATION (TOP VIEW) HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VHV GND 1 GND 2 CL NC LS NC R/L DIN VCC , 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NC : No-connection pin 60-Pin Plastic SSOP MSC1162A 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 HVO 40 HVO 39 HVO 38 HVO 37 HVO 36 HVO 35 HVO 34 HVO 33 HVO 32 HVO 31 HVO 30 HVO 29 HVO 28 HVO 27 HVO 26 HVO 25 HVO 24 HVO 23 HVO 22 HVO 21 VHV GND 1 GND 2 NC CHG NC CLK NC DOUT VCC 5/14 www.DataSheet4U.com ¡ Semiconductor MSC1162A PIN DESCRIPTION Symbol CLK Type I Description Shift register clock input pin. Shift register reads data through DIN while the CLK pin is low state and the data in the shift register is shifted from one stage to the next stage at the rising edge of the clock. Serial data input pin of the shift register. Display data (positive logic) is input in through the DIN pin synchronization with clock. Serial data output pin of the shift register. Data is output through the DOUT pin in synchronization with the CLK signal. When R/L = High, the data of PO40 in the shift register is output through the DOUT pin. When R/L = Low, the data of PO1 pin in the shift register is output through the DOUT pin. Latch strobe input pin When LS is high, the parallel output data (PO1-40) of the shift register read out. When LS goes from high to low, the parallel output data (PO1-40) of the shift register is held. Clear input pin with a built-in pull-up resistor The CL pin is normally being set high. If the CL pin is high and the CHG pin is low, the driver outputs (HV01 to HV40) are in phase with the corresponding latch outputs (O1 to O40). If the CL pin is high and the CHG pin is high, the driver outputs (HV01 to HV40) are high irrespective of the states of the latch outputs. If the CL pin is set low, the driver outputs are driven low irrespective of the states of the CHG pin and latch output... |
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