Maker : Texas Instruments
Part No. : CDCUA877

Datasheet PDF : CDCUA877.pdf
Cross Reference : CDCUA877 Cross Reference
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CDCUA877 www.ti.com SCAS769A – AUGUST 2006 – REVISED JUNE 2007 1.8-V PHASE LOCK LOOP CLOCK DRIVER FEATURES • • • • • • • • 1.8-V/1.9-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II) Applications Spread Spectrum Clock Compatible Operating Frequency: 125 MHz to 410 MHz Application Frequency: 160 MHz to 410 MHz Low Current Consumption: <200 mA Typ Low Jitter (Cycle-Cycle): ±40 ps Low Output Skew: 35 ps Stabilization Time <6 μs • • • Distributes One Differential Clock Input to Ten Differential Outputs 52-Ball μBGA (MicroStar Junior™ BGA, 0,65-mm pitch) External Feedback Pins (FBIN, FBIN) are Used to Synchronize the Outputs to the Input Clockst Meets or Exceeds CUA877/CAU878 Specification PLL Standard for PC2-3200/4300/5300/6400o Fail-Safe Inputs • • DESCRIPTION The CDCUA877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time. The CDCUA877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from –40°C to 85°C). AVAILABLE OPTIONS TA –40°C to 85°C (1) 52-Ball BGA (1) CDCUA877ZQL For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MicroStar Junior is a trademark of Texas Instruments. www.DataSheet4U.com PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2007, Texas Instruments Incorporated CDCUA877 www.ti.com SCAS769A – AUGUST 2006 – REVISED JUNE 2007 Submit Documentation Feedback www.DataSheet4U.com 2 CDCUA877 www.ti.com SCAS769A – AUGUST 2006 – REVISED JUNE 2007 Table 1. Terminal Functions NAME AGND AVDD CK CK FBIN FBIN FBOUT FBOUT OE OS GND BGA G1 H1 E1 F1 E6 F6 H6 G6 F5 D5 B2, B3, B4, B5, C2, C5, H2, H5, J2, J3, J4, J5 D2, D3, D4, E2, E5, F2, G2, G3, G4, G5 MLF 7 8 4 5 27 26 24 25 22 21 10 I I I I O O I I I/O Analog ground Analog power Clock input with a (10 kΩ to 100 kΩ) pulldown resistor Complementary clock input with a (10 kΩ to 100 kΩ) pulldown resistor Feedback clock input Complementary feedback clock input Feedback clock output Complementary feedback clock output Output enable (asynchronous) Output select (tied to GND or VDD) Ground DESCRIPTION VD...

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