Maker : Eon
Part No. : EN25F80

  Datasheet PDF : EN25F80.pdf
  Cross Reference : EN25F80 Cross Reference
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Shortcut : EN25F80 

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www.DataSheet4U.com EN25F80 EN25F80 8 Mbit Serial Flash Memory with 4Kbytes Uniform Sector FEATURES • Single power supply operation - Full voltage range: 2.7-3.6 volt • 8 Mbit Serial Flash - 8 M-bit/1024 K-byte/4096 pages - 256 bytes per programmable page • High performance - 100MHz clock rate • Low power consumption - 5 mA typical active current - 1 μA typical power down current • Uniform Sector Architecture: 256 sectors of 4-Kbyte 16 blocks of 64-Kbyte Any sector or block can be erased individually - Write Protect all or portion of memory via software - Enable/Disable protection with WP# pin • High performance program/erase speed Page program time: 1.5ms typical Sector erase time: 150ms typical Block erase time 800ms typical Chip erase time: 10 Seconds typical • Lockable 256 byte OTP security sector • Minimum 100K endurance cycle • Package Options 8 pins SOP 200mil body width 8 contact VDFN 8 pins PDIP All Pb-free packages are RoHS compliant • Software and Hardware Write Protection: • Commercial and industrial temperature Range GENERAL DESCRIPTION The EN25F80 is a 8M-bit (1024K-byte) Serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The EN25F80 is designed to allow either single Sector at a time or full chip erase operation. The EN25F80 can be configured to protect part of the memory as the software protected mode. The device can sustain a minimum of 100K program/erase cycles on each sector. This Data Sheet may be revised by subsequent versions 1 or modifications due to changes in technical specifications. ©2004 Eon Silicon Solution, Inc., www.essi.com.tw Rev. D, Issue Date: 2007/05/16 www.DataSheet4U.com EN25F80 Figure.1 CONNECTION DIAGRAMS 8 - LEAD SOP 8 - CONTACT VDFN Figure 2. BLOCK DIAGRAM This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 2 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw Rev. D, Issue Date: 2007/05/16 www.DataSheet4U.com EN25F80 SIGNAL DESCRIPTION Serial Data Input (DI) The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK) input pin. Serial Data Output (DO) The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from (shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin. Serial Clock (CLK) The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Mode") Chip Select (CS#) The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or status register cycle is in progress. When CS# is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, CS# must transition from high to low before a new instruction will be accepted. Hold (HOLD#) The HOLD pin allows the device to be paused while it is actively selected. When HOLD is brought low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). The hold function can be useful when multiple devices are sharing the same SPI signals. Write Protect (WP#) The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (BP0, BP1and BP2) bits and Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. Table 1. PI...

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