Maker : InnovASIC
Part No. : IA63484

  Datasheet PDF : IA63484.pdf
  Cross Reference : IA63484 Cross Reference
  Buy Component : IA63484 Find Stock and Price

Shortcut : IA63484  IA63484-PLC68I 

Product Information

IA63484 Advanced CRT Controller FEATURES • Preliminary Data Sheet innovASIC • • • • • • • • • • • High-speed graphics - Drawing rate: 200 ns/pixel max (color drawing) - Commands: 38 commands including 23 graphic drawing commands: Dot, Line, Rectangle, Poly-line, Polygon, Circle, Ellipse, Paint, Copy, etc. - Colors: 16 bits/word: 1,2,4,8,16 bits/pix el (5 types) monochrome to 64k colors max - Pattern RAM: 32 bytes - Converts logical X-Y coordinate to physical address - Color operation and conditional drawing - Drawing area control for hardware clipping and hitting Large frame-memory space - Maximum 2 Mbytes graphic memory and 128 kbytes character memory separate from MPU memory. - Maximum Resolution: 4096 x 4096 pixels (1 bit/pixel mode) CRT display control - Split Screens: three displays and one window Zoom: 1 to 16 times Scroll: vertical and horizontal Interleaved access mode for flashless display and superimposition External synchronization between ARTCs or between ACRTC and external device (TV system or other controller. DMA interface Two programmable cursors Three Scan modes - Non-interlaced - Interlace sync - Interlace sync and video Interrupt request to MPU 256 characters/line 32 raster/ line, 4096 rasters/screen Maximum clock frequency: 20MHz CMOS, single +5V power supply The IA63484 is a "plug-and-play" drop-in replacement for the original Hitachi© HD63484. This replacement IC has been developed using innovASIC’s MILESTM, or Managed IC Lifetime Extension System, cloning technology. This technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible with the original IC. MILESTM captures the design of a clone so it can be produced even as silicon technology advances. MILESTM also verifies the clone against the original IC so that even the "undocumented features" are duplicated. This data sheet documents all necessary engineering information about the IA63484 including functional and I/O descriptions, electrical characteristics, and applicable timing. Copyright © 2003 innovASIC The End of Obsolescence™ ENG 21101041201 Page 1 of 32 www.innovasic.com Customer Support: 1−888−824−4184 IA63484 Advanced CRT Controller 68 Pin Package: PLCC PINOUT Pin Arrangement: Preliminary Data Sheet dreq_n done_n(O,D) res_n rs cs_n rw_n cud2_n cud1_n Vcc lpstb disp1_n disp2_n mad0(T) mad1(T) mad2(T) mad3(T) mad4(T) dack_n dtack_n(T) irq(O,D) hsync_n vsync_n Vcc exsync_n Vss Vss d0(T) d1(T) d2(T) d3(T) d4(T) d5(T) d6(T) d7(T) 9 1 68 60 IA63484 27 44 chr mrd draw_n as_n mcyc Vss Vss clk_2 Vcc mad5(T) mad6(T) mad7(T) mad8(T) mad9(T) mad10(T) mad11(T) mad12(T) O,D: Open Drain T: Three State Copyright © 2003 innovASIC The End of Obsolescence™ d8(T) d9(T) d10(T) d11(T) d12(T) d13(T) d14(T) d15(T) Vss ra4 ma_ra19_3 ma_ra18_2 ma_ra17_1 ma_ra16_0 mad15(T) mad14(T) mad13(T) ENG 21101041201 Page 2 of 32 www.innovasic.com Customer Support: 1−888−824−4184 IA63484 Advanced CRT Controller BLOCK DIAGRAM Figure 1: System Block Diagram Preliminary Data Sheet Figure 2 illustrates the IA63484 system environment. The following paragraphs will further describe the system block diagram and design in more detail. res_n MPU (8/16b) irq_n d[15:0] as_n ma[19:16] L dtack_n mrd cs_n FRAME BUFFER 2MB, MAX rs mad[15:0] rw_n SYSTEM MEMORY dreq_n ACRTC disp2_n disp1_n cud2_n dack_n ADDRESS CONTROL cud1_n DATA DOT SHIFTER done_n lpstb clk_2 exsync_n Vss DMAC Vcc vsync_n CRT VIDEO SIGNAL hsync_n Copyright © 2003 innovASIC The End of Obsolescence™ ENG 21101041201 Page 3 of 32 www.innovasic.com Customer Support: 1−888−824−4184 IA63484 Advanced CRT Controller I/O SIGNAL DESCRIPTION: Preliminary Data Sheet The diagram below describes the I/O characteristics for each signal on the IC. The signal names correspond to the signal names on the pinout diagrams provided. I/O Characteristics: Signal Name res_n d[15,0] rw_n cs_n rs dtack_n irq_n d...

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