Maker : Infineon Technologies AG
Part No. : IPB09N03LA

  Datasheet PDF : IPB09N03LA.pdf
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Shortcut : IPB09N03LA  IPB09N03LAG 

Product Information

IPB09N03LA IPI09N03LA, IPP09N03LA OptiMOS®2 Power-Transistor Features • Ideal for high-frequency dc/dc converters • N-channel • Logic level • Excellent gate charge x R DS(on) product (FOM) • Very low on-resistance R DS(on) • Superior thermal resistance • 175 °C operating temperature • dv /dt rated P-TO263-3-2 Product Summary V DS R DS(on),max (SMD version) ID 25 8.9 50 V mΩ A P-TO262-3-1 P-TO220-3-1 Type IPB09N03LA IPI09N03LA IPP09N03LA Package P-TO263-3-2 P-TO262-3-1 P-TO220-3-1 Ordering Code Q67042-S4151 Q67042-S4152 Q67042-S4153 Marking 09N03LA 09N03LA 09N03LA Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Continuous drain current Symbol Conditions ID T C=25 °C1) T C=100 °C Pulsed drain current Avalanche energy, single pulse Reverse diode dv /dt Gate source voltage3) Power dissipation Operating and storage temperature IEC climatic category; DIN IEC 68-1 I D,pulse E AS dv /dt V GS P tot T j, T stg T C=25 °C T C=25 °C2) I D=45 A, R GS=25 Ω I D=50 A, V DS=20 V, di /dt =200 A/µs, T j,max=175 °C Value 50 46 350 75 6 ±20 63 -55 ... 175 55/175/56 mJ kV/µs V W °C Unit A Rev. 1.3 page 1 2003-12-18 IPB09N03LA IPI09N03LA, IPP09N03LA Parameter Symbol Conditions min. Thermal characteristics Thermal resistance, junction - case SMD version, device on PCB R thJC R thJA minimal footprint 6 cm2 cooling area4) Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current V (BR)DSS V GS=0 V, I D=1 mA V GS(th) I DSS V DS=V GS, I D=20 µA V DS=25 V, V GS=0 V, T j=25 °C V DS=25 V, V GS=0 V, T j=125 °C Gate-source leakage current Drain-source on-state resistance I GSS R DS(on) V GS=20 V, V DS=0 V V GS=4.5 V, I D=30 A V GS=4.5 V, I D=30 A, SMD version V GS=10 V, I D=30 A V GS=10 V, I D=30 A, SMD version Gate resistance Transconductance RG g fs |V DS|>2|I D|R DS(on)max, I D=30 A 25 1.2 1.6 0.1 2 1 µA V 2.4 62 40 K/W Values typ. max. Unit 21 10 10 12.4 12.1 7.7 7.4 1 42 100 100 15.5 15.1 9.2 8.9 Ω S nA mΩ 1) Current is limited by bondwire; with an R thJC=2.4 K/W the chip is able to carry 64 A. See figure 3 T j,max=150 °C and duty cycle D <0.25 for V GS<-5 V 2) 3) 4) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.3 page 2 2003-12-18 IPB09N03LA IPI09N03LA, IPP09N03LA Parameter Symbol Conditions min. Dynamic characteristics Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Gate Charge Characteristics5) Gate to source charge Gate charge at threshold Gate to drain charge Switching charge Gate charge total Gate plateau voltage Gate charge total, sync. FET Output charge Reverse Diode Diode continous forward current Diode pulse current Diode forward voltage IS I S,pulse V SD T C=25 °C V GS=0 V, I F=50 A, T j=25 °C V R=15 V, I F=I S, di F/dt =400 A/µs 0.98 50 350 1.2 V A Q gs Q g(th) Q gd Q sw Qg V plateau Q g(sync) Q oss V DS=0.1 V, V GS=0 to 5 V V DD=15 V, V GS=0 V V DD=15 V, I D=25 A, V GS=0 to 5 V 4.4 2.0 3.1 5.5 10 3.5 9 11 5.8 2.6 4.7 7.9 14 12 15 V nC nC C iss C oss Crss t d(on) tr t d(off) tf V DD=15 V, V GS=10 V, I D=25 A, R G=2.7 Ω V GS=0 V, V DS=15 V, f =1 MHz 1240 530 81 9 88 22 4.2 1649 704 122 13 132 33 6 ns pF Values typ. max. Unit Reverse recovery charge Q rr - - 10 nC 5) See figure 16 for gate charge parameter definition Rev. 1.3 page 3 2003-12-18 IPB09N03LA IPI09N03LA, IPP09N03LA 1 Power dissipation P tot=f(T C) 2 Drain current I D=f(T C); V GS≥10 V 70 60 60 50 40 P tot [W] 40 30 I D [A] 20 0 0 50 100 150 200 0 50 100 150 200 20 10 0 T C [°C] T C [°C] 3 Safe operation area I D=f(V DS); T C=25 °C; D =0 parameter: t p 1000 4 Max. transient thermal impedance Z thJC=f(t p) parameter: D =t p/T 10 limited by on-state resistance 1 ...

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