Maker : Philips Semiconductors
Part No. : J111

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Product Information

DISCRETE SEMICONDUCTORS DATA SHEET J111; J112; J113 N-channel silicon field-effect transistors Product specification File under Discrete Semiconductors, SC07 July 1993 Philips Semiconductors Product specification N-channel silicon field-effect transistors DESCRIPTION Symmetrical silicon n-channel junction FETs in plastic TO-92 envelopes. They are intended for applications such as analog switches, choppers, commutators etc. FEATURES • High speed switching • Interchangeability of drain and source connections • Low RDS on at zero gate voltage PINNING 1 = gate 2 = source 3 = drain Note: Drain and source are interchangeable. 1 handbook, halfpage 2 3 J111; J112; J113 g MAM042 d s Fig.1 Simplified outline and symbol, TO-92. QUICK REFERENCE DATA J111 Drain-source voltage Drain current VDS = 15 V; VGS = 0 Total power dissipation up to Tamb = 50 °C Gate-source cut-off voltage VDS = 5 V; ID = 1 µA Drain-source on-state resistance VDS = 0.1 V; VGS = 0 RDS on max. 30 50 100 Ω −VGS off min. max. 3 10 1 5 0.5 3 V V Ptot max. 400 400 400 mW IDSS min. 20 5 2 mA ±VDS max. 40 J112 40 J113 40 V July 1993 2 Philips Semiconductors Product specification N-channel silicon field-effect transistors RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Drain-source voltage Gate-source voltage Gate-drain voltage Gate forward current (DC) Total power dissipation up to Tamb = 50 °C Storage temperature range Junction temperature THERMAL RESISTANCE From junction to ambient in free air STATIC CHARACTERISTICS Tj = 25 °C unless otherwise specified J111 Gate reverse current −VGS = 15 V; VDS = 0 Drain cut-off current VDS = 5 V; −VGS = 10 V Drain saturation current VDS = 15 V; VGS = 0 Gate-source breakdown voltage −IG = 1 µA; VDS = 0 Gate-source cut-off voltage VDS = 5 V; ID = 1 µA Drain-source on-state resistance VDS = 0.1 V; VGS = 0 RDSon max. 30 −VGS off min. max. 3 10 −V(BR)GSS min. 40 IDSS min. 20 −IDSX max. 1 −IGSS max. 1 Rth j-a = Ptot Tstg Tj max. max. ±VDS −VGSO −VGDO IG max. max. max. max. J111; J112; J113 40 V 40 V 40 V 50 mA 400 mW −65 to + 150 °C 150 °C 250 K/W J112 1 1 5 40 1 5 50 J113 1 1 2 40 0.5 3 100 nA nA mA V V V Ω July 1993 3 Philips Semiconductors Product specification N-channel silicon field-effect transistors DYNAMIC CHARACTERISTICS Tj = 25 °C unless otherwise specified Input capacitance VDS = 0; −VGS = 10 V; f = 1 MHz VDS = −VGS = 0; f = 1 MHz Feedback capacitance VDS = 0; −VGS = 10 V; f = 1 MHz Switching times test conditions VDD = 10 V; VGS = 0 to VGSoff −VGS off = 12 V; RL = 750 Ω for J111 −VGS off = 7 V; RL = 1550 Ω for J112 −VGS off = 5 V; RL = 3150 Ω for J113 Rise time Turn-on time Fall time Turn-off time tr ton tf toff typ. typ. typ. typ. Crs typ. Cis Cis typ. typ. max. J111; J112; J113 6 pF 22 pF 28 pF 3 pF 6 ns 13 ns 15 ns 35 ns VGS = 0 V ok, halfpage 10% VDD 10 nF 50 Ω 10 µF RL 1 µF Vi 90% toff tf 90% Vo MBK289 VGS off DUT 50 Ω SAMPLING SCOPE 50 Ω ton tr 10% MBK288 Fig.2 Switching times test circuit. Fig.3 Input and output waveforms. July 1993 4 Philips Semiconductors Product specification N-channel silicon field-effect transistors PACKAGE OUTLINE Plastic single-ended leaded (through hole) package; 3 leads J111; J112; J113 SOT54 c E d A L b 1 D 2 e1 e 3 b1 L1 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 5.2 5.0 b 0.48 0.40 b1 0.66 0.56 c 0.45 0.40 D 4.8 4.4 d 1.7 1.4 E 4.2 3.6 e 2.54 e1 1.27 L 14.5 12.7 L1(1) 2.5 Note 1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities. OUTLINE VERSION SOT54 REFERENCES IEC JEDEC TO-92 EIAJ SC-43 EUROPEAN PROJECTION ISSUE DATE 97-02-28 July 1993 5 Philips Semiconductors Product specification N-channel silicon field-effect transistors DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Shor...

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