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Part No. : J112

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by J112/D JFET Chopper Transistor N–Channel — Depletion 1 DRAIN 3 GATE J112 2 SOURCE MAXIMUM RATINGS Rating Drain – Gate Voltage Gate – Source Voltage Gate Current Total Device Dissipation @ TA = 25°C Derate above 25°C Lead Temperature Operating and Storage Junction Temperature Range Symbol VDG VGS IG PD TL TJ, Tstg Value – 35 – 35 50 350 2.8 300 – 65 to +150 Unit Vdc Vdc mAdc mW mW/°C °C °C CASE 29–04, STYLE 5 TO–92 (TO–226AA) 1 2 3 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Max Unit OFF CHARACTERISTICS Gate – Source Breakdown Voltage (IG = –1.0 µAdc) Gate Reverse Current (VGS = –15 Vdc) Gate Source Cutoff Voltage (VDS = 5.0 Vdc, ID = 1.0 µAdc) Drain–Cutoff Current (VDS = 5.0 Vdc, VGS = –10 Vdc) V(BR)GSS IGSS VGS(off) ID(off) 35 — – 1.0 — — – 1.0 – 5.0 1.0 Vdc nAdc Vdc nAdc ON CHARACTERISTICS Zero–Gate–Voltage Drain Current(1) (VDS = 15 Vdc) Static Drain–Source On Resistance (VDS = 0.1 Vdc) Drain Gate and Source Gate On–Capacitance (VDS = VGS = 0, f = 1.0 MHz) Drain Gate Off–Capacitance (VGS = –10 Vdc, f = 1.0 MHz) Source Gate Off–Capacitance (VGS = –10 Vdc, f = 1.0 MHz) 1. Pulse Width = 300 µs, Duty Cycle = 3.0%. IDSS rDS(on) Cdg(on) + Csg(on) Cdg(off) Csg(off) 5.0 — — — 50 28 mAdc Ω pF — — 5.0 5.0 pF pF (Replaces J111/D) Motorola Small–Signal Transistors, FETs and Diodes Device Data © Motorola, Inc. 1997 1 J112 TYPICAL SWITCHING CHARACTERISTICS 1000 t d(on), TURN–ON DELAY TIME (ns) 500 200 100 50 20 10 5.0 RK = 0 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 50 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 50 RK = RD′ TJ = 25°C VGS(off) = 7.0 V t r , RISE TIME (ns) 1000 500 200 100 50 20 10 5.0 RK = 0 RK = RD′ TJ = 25°C VGS(off) = 7.0 V Figure 1. Turn–On Delay Time Figure 2. Rise Time 1000 t d(off) , TURN–OFF DELAY TIME (ns) 500 200 100 50 20 10 5.0 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) RK = 0 RK = RD′ TJ = 25°C VGS(off) = 7.0 V t f , FALL TIME (ns) 1000 500 200 100 50 20 10 5.0 2.0 RK = 0 RK = RD′ TJ = 25°C VGS(off) = 7.0 V 20 30 50 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 50 Figure 3. Turn–Off Delay Time Figure 4. Fall Time NOTE 1 +VDD RD SET VDS(off) = 10 V INPUT RGEN 50 Ω 50 Ω VGEN RK RT OUTPUT RGG VGG 50 Ω INPUT PULSE tr ≤ 0.25 ns tf ≤ 0.5 ns PULSE WIDTH = 2.0 µs DUTY CYCLE ≤ 2.0% RGG & RK RD (R ) 50) + RRD) TRT ) 50 D Figure 5. Switching Time Test Circuit The switching characteristics shown above were measured using a test circuit similar to Figure 5. At the beginning of the switching interval, the gate voltage is at Gate Supply Voltage (–VGG). The Drain–Source Voltage (VDS) is slightly lower than Drain Supply Voltage (VDD) due to the voltage divider. Thus Reverse Transfer Capacitance (Crss) or Gate–Drain Capacitance (Cgd) is charged to VGG + VDS. During the turn–on interval, Gate–Source Capacitance (C gs) discharges through the series combination of RGen and RK. Cgd must discharge to VDS(on) through RG and RK in series with the parallel combination of effective load impedance (R′ D ) and Drain–Source Resistance (rds). During the turn–off, this charge flow is reversed. Predicting turn–on time is somewhat difficult as the channel resistance rds is a function of the gate–source voltage. While Cgs discharges, VGS approaches zero and rds decreases. Since Cgd discharges through rds, turn–on time is non–linear. During turn–off, the situation is reversed with rds increasing as Cgd charges. The above switching curves show two impedance conditions; 1) RK is equal to RD, which simulates the switching behavior of cascaded stages where the driving source impedance is normally the load impedance of the previous stage, and 2) RK = 0 (low impedance) the driving sou...

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