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P-channel silicon field-effect transistorsMaker : Philips Semiconductors
Shortcut : J174 J174 J174 J174 J174 J175 J175 J175 J175 J175 J176 J176 J176 J176 J176 J177 J177 J177 J177 J177 |
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DISCRETE SEMICONDUCTORS DATA SHEET J174; J175; J176; J177 P-channel silicon field-effect transistors Product specification File under Discrete Semiconductors, SC07 April 1995 Philips Semiconductors Product specification P-channel silicon field-effect transistors DESCRIPTION Silicon symmetrical p-channel junction FETs in a plastic TO-92 envelope and intended for application with analog switches, choppers, commutators etc. A special feature is the interchangeability of the drain and source connections. PINNING 1 = 2 = 3 = source gate drain 1 handbook, halfpage 2 3 g MAM388 J174; J175; J176; J177 d s Note: Drain and source are interchangeable. Fig.1 Simplified outline and symbol, TO-92. QUICK REFERENCE DATA Drain-source voltage Gate-source voltage Gate current Total power dissipation up to Tamb = 50 °C Ptot max. J174 Drain current −VDS = 15 V; VGS = 0 Drain-source ON-resistance −VDS = 0.1 V; VGS = 0 RDS on max. 85 125 250 300 Ω −IDSS min. max. 20 135 7 70 2 35 1.5 20 mA mA 400 J175 J176 J177 mW ± VDS VGSO −IG max. max. max. 30 30 50 V V mA April 1995 2 Philips Semiconductors Product specification P-channel silicon field-effect transistors RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Drain-source voltage Gate-source voltage Gate-drain voltage Gate current (DC) Total power dissipation up to Tamb = 50 °C Storage temperature range Junction temperature THERMAL RESISTANCE From junction to ambient in free air STATIC CHARACTERISTICS Tj = 25 °C unless otherwise specified Gate cut-off current VGS = 20 V; VDS = 0 Drain cut-off current −VDS = 15 V; VGS = 10 V Drain current −VDS = 15 V; VGS = 10 V Gate-source breakdown voltage IG = 1 µA; VDS = 0 Gate-source cut-off voltage −ID = 10 nA; VDS = −15 V Drain-source ON-resistance −VDS = 0.1 V; VGS = 0 RDSon max. 85 125 VGS off min. max. 5 10 3 6 V(BR)GSS min. 30 30 −IDSS min. max. 20 135 7 70 −IDSX max. 1 1 IGSS max. 1 1 J174 J175 Rth j-a = Ptot Tstg Tj max. max. ± VDS VGSO VGDO −IG max. max. max. max. J174; J175; J176; J177 30 30 30 50 400 −65 to +150 150 V V V mA mW °C °C 250 K/W J176 J177 1 1 2 35 30 1 4 250 1 nA 1 nA 1.5 mA 20 mA 30 V 0.8 V 2.25 V 300 Ω April 1995 3 Philips Semiconductors Product specification P-channel silicon field-effect transistors DYNAMIC CHARACTERISTICS Tj = 25 °C unless otherwise specified Input capacitance, f = 1 MHz VGS = 10 V; VDS = 0 V VGS = VDS = 0 Feedback capacitance, f = 1 MHz VGS = 10 V; VDS = 0 V Switching times (see Fig.2 + 3) Delay time Rise time Turn-on time Storage time Fall time Turn-off time Test conditions: td tr ton ts tf toff −VDD VGS off RL VGS on typ. typ. typ. typ. typ. typ. Crs typ. J174 2 5 7 5 10 15 10 12 560 0 4 J175 5 10 15 10 20 30 6 8 1200 0 Cis Cis typ. typ. 8 30 J174; J175; J176; J177 pF pF pF J176 J177 15 20 35 15 20 35 6 6 0 20 ns 25 ns 45 ns 20 ns 25 ns 45 ns 6 V 3 V 0 V 2000 2900 Ω handbook, halfpage −VDD 50 Ω Vout RL Vin 50 Ω MBK292 VGSoff INPUT 10% 90% 10% OUTPUT 90% tf ts td 10% D.U.T 90% tr MBK293 Fig.2 Switching times test circuit. Fig.3 Input and output waveforms; td + tr = ton ; ts + tf = toff. April 1995 4 Philips Semiconductors Product specification P-channel silicon field-effect transistors PACKAGE OUTLINE Plastic single-ended leaded (through hole) package; 3 leads J174; J175; J176; J177 SOT54 c E d A L b 1 D 2 e1 e 3 b1 L1 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 5.2 5.0 b 0.48 0.40 b1 0.66 0.56 c 0.45 0.40 D 4.8 4.4 d 1.7 1.4 E 4.2 3.6 e 2.54 e1 1.27 L 14.5 12.7 L1(1) 2.5 Note 1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities. OUTLINE VERSION SOT54 REFERENCES IEC JEDEC TO-92 EIAJ SC-43 EUROPEAN PROJECTION ISSUE DATE 97-02-28 April 1995 5 Philips Semiconductors Product specification P-channel silicon field-effect transistors DEFINITIONS Data sheet status Objective specificat... |
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