Maker : Clare Inc.
Part No. : M-8880

  Datasheet PDF : M-8880.pdf
  Cross Reference : M-8880 Cross Reference
  Buy Component : M-8880 Find Stock and Price

Shortcut : M-8880  M-8888  M-8888-01  M-8888-01P  M-8888-01SM  M-8888-01T 

Product Information

M-8880 DTMF Transceiver · · · · · · · · · · · · · Advanced CMOS technology for low power consumption and increased noise immunity Complete DTMF transmitter/receiver in a single chip Standard 6500/6800 series microprocessor port Central office quality and performance Adjustable guard time Automatic tone burst mode Call progress mode Single +5 Volt power supply 20-pin DIP and SOIC packages 2 MHz microprocessor port operation Inexpensive 3.58 MHz crystal No continuous f2 clock required, only strobe Applications include: paging systems, repeater systems/mobile radio, interconnect dialers, PBX systems, computer systems, fax machines, pay telephones, credit card verification Figure 1 Pin Diagram Functional Description M-8880 functions consist of a high-performance DTMF receiver with an internal gain setting amplifier and a DTMF generator that contains a tone burst counter for generating precise tone bursts and pauses. The call progress mode, when selected, allows the detection of call progress tones. A standard 6500/6800 series microprocessor interface allows access to an internal status register, two control registers, and two data registers. Input Configuration The input arrangement consists of a differential input operational amplifier and bias sources (VREF) for biasing the amplifier inputs at VDD/2. Provisions are made for the connection of a feedback resistor to the op-amp output (GS) for gain adjust- The M-8880 is a complete DTMF Transmitter/Receiver that features adjustable guard time, automatic tone burst mode, call progress mode, and a fully compatible 6500/6800 microprocessor interface. The receiver portion is based on the industry standard M-8870 DTMF Receiver, while the transmitter uses a switched-capacitor digital-to-analog converter for low-distortion, highly accurate DTMF signaling. Tone bursts can be transmitted with precise timing by making use of the automatic tone burst mode. To analyze call progress tones, a call progress filter can be selected by an external microprocessor. Figure 2 Block Diagram 40-406-00012, Rev. G www.clare.com Page 1 M-8880 Figure 3 Single-Ended Input Configuration Figure 4 Differential Input Configuration ment. In a single-ended configuration, the input pins should be connected as shown in Figure 3. Figure 4 shows the necessary connections for a differential input configuration. Receiver Section The low and high group tones are separated by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass filters with bandwidths that correspond to the low and high group frequencies listed in Table 2. The low group filter incorporates notches at 350 and 440 Hz, providing excellent dial tone rejection. Each filter output is followed by a single-order switched capacitor filter that smooths the signals prior to limiting. Limiting is performed by high-gain comparators with hysteresis to prevent detection of unwanted low-level signals. The comparator outputs provide full-rail logic swings at the incoming DTMF signal frequencies. A decoder employs digital counting techniques to determine the frequencies of the incoming tones, and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals (such as voice), while tolerating small deviations in frequency. The algorithm provides an optimum combination of immunity to talkoff with tolerance to interfering frequencies (third tones) and noise. When the detector recognizes the presence of two valid tones (referred to as “signal condition”), the early steering (ESt) output goes to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state. Steering Circuit: Before a decoded tone pair is registered, the receiver checks for a valid signal duration (referred to as “character recognition condition”). This check is performed by an external RC time constant driven by ESt. A logic high o...

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