Maker : ETC
Part No. : M1010-01

  Datasheet PDF : M1010-01.pdf
  Cross Reference : M1010-01 Cross Reference
  Buy Component : M1010-01 Find Stock and Price

Shortcut : M1010-01 

Product Information

Integrated Circuit Systems, Inc. Preliminary Information M1010-01 VCSO BASED CLOCK JITTER ATTENUATOR PIN ASSIGNMENT (9 x 9 mm SMT) FIN_SEL1 GND NC DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC FIN_SEL0 SEL0 SEL1 SEL2 NC VCC DNC DNC DNC 27 26 25 24 23 22 21 20 19 GENERAL DESCRIPTION The M1010-01 is a VCSO (Voltage Controlled SAW Oscillator) based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation. The device is ideal for generating the transmit reference clock for OC-12 and OC-48 optical network systems supporting 622 2,488 MHz rates. It can serve to jitter attenuate a stratum reference clock or a recovered clock in loop timing mode. The M1010-01 module includes a proprietary SAW (surface acoustic wave) delay line as part of the VCSO. This results in a high frequency, high-Q, low phase noise oscillator that assures low intrinsic output jitter. 28 29 30 31 32 33 34 35 36 M1010 (Top View) 18 17 16 15 14 13 12 11 10 VCC NC nFOUT FOUT GND NC NC VCC GND FEATURES ◆ Ideal for OC-12/48 data clock ◆ Integrated SAW delay line ◆ Output frequencies from 150 to 175 MHz (Specify VCSO output frequency at time of order) ◆ Low phase jitter of 0.5 ps rms, typical (12kHz to 20MHz) ◆ LVPECL clock output ◆ Pin-selectable feedback and reference divider ratios, no programming required ◆ Scalable dividers provide further adjustment of loop bandwidth as well as jitter tolerance ◆ Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL ◆ Single 3.3V power supply ◆ Small 9 x 9 mm SMT (surface mount) package Figure 1: Pin Assignment Example I/O Clock Frequency Combinations Using M1010-01-155.5200 Frequency Input (Mfin) Ratio 8 2 1 Input Reference Clock (MHz) 19.44 77.76 155.52 Output Clock MHz 155.52 Table 1: Example I/O Clock Frequency Combinations SIMPLIFIED BLOCK DIAGRAM M1010 DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_SEL 3 2 0 R Div 1 M Div Mfin Div VCSO Loop Filter GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN 1 2 3 4 5 6 7 8 9 SEL2:0 FIN_SEL1:0 Divider LUT Mfin Divider LUT FOUT nFOUT Figure 2: Simplified Block Diagram M1010-01 Datasheet Rev 0.4 M1010-01 VCSO Based Clock Jitter Attenuator Revised 29Sep2003 ● Integrated Circuit Systems, Inc. Communications Modules ● w w w. i c s t . c o m ● tel (508) 852-5400 Integrated Circuit Systems, Inc. M1010-01 VCSO BASED CLOCK JITTER ATTENUATOR Preliminary Information DETAILED BLOCK DIAGRAM RLOOP CLOOP RPOST CPOST CPOST RLOOP CLOOP RPOST nOP_OUT nVC VC External Loop Filter Components M1010 MUX OP_IN Phase Detector nOP_IN OP_OUT DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_SEL 3 RIN 0 R Div 1 RIN Loop Filter Amplifier Phase Locked Loop (PLL) SAW Delay Line Phase Shifter VCSO M Div Mfin Divider SEL2:0 Divider LUT Mfin Divider LUT FOUT nFOUT FIN_SEL1:0 2 Figure 3: Detailed Block Diagram PIN DESCRIPTIONS Number 1, 2, 3, 10, 14, 26 4 9 5 8 6 7 11, 18, 19, 33 12, 13, 17, 25, 32 15 16 20 21 22 23 24 27 28 29 30 31 34, 35, 36 Name GND OP_IN nOP_IN nOP_OUT OP_OUT nVC VC VCC NC FOUT nFOUT nDIF_REF1 DIF_REF1 REF_SEL nDIF_REF0 DIF_REF0 FIN_SEL1 FIN_SEL0 SEL0 SEL1 SEL2 DNC I/O Configuration Description Ground Input Output Input Power Output Input Input Input Input Input No internal terminator Internal pull-UP resistor1 Internal pull-down resistor 1 Power supply ground connections. External loop filter connections. See Figure 4, External Loop Filter, on pg. 4. Power supply connection, connect to +3.3V. No internal connection. Clock output pairs. Differential LVPECL. Reference clock input pair. Differential LVPECL or LVDS. Reference clock input selection. LVCMOS/LVTTL: Logic 1 selects DIF_REF1, nDIF_REF1. Logic 0 selects DIF_REF0, nDIF_REF0. Reference clock input pair. Differential LVPECL or LVDS. Internal pull-down resistor1 Internal pull-UP resistor1 Internal pull-down resistor 1 Input clock frequency selection. LVCMOS/LVTTL. Internal pull-down resistor1 See Ta...

Link URL