Maker : Integrated Circuit Systems
Part No. : M1040-11I156.2500

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Product Information

Integrated Circuit Systems, Inc. Preliminary Information M1040 VCSO BASED CLOCK PLL WITH AUTOSWITCH PIN ASSIGNMENT (9 x 9 mm SMT) MR_SEL2 GND AUTO DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC MR_SEL1 MR_SEL0 REF_ACK LOL NBW VCC DNC DNC DNC 27 26 25 24 23 22 21 20 19 GENERAL DESCRIPTION The M1040 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock protection, frequency translation and jitter attenuation in OC-12/48 class optical networking systems. It features dual differential inputs with two modes of input selection: manual and automatic upon clock failure. The clock multiplication ratios and output divider ratio are pin selectable. This device provides two outputs. External loop components allow the tailoring of PLL loop response. FEATURES ◆ Integrated SAW (surface acoustic wave) delay line; low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz) ◆ Output frequencies of 62.5 to 175 MHz *; Two differential LVPECL outputs (CML, LVDS options available) ◆ Loss of Lock (LOL) indicator output ◆ Narrow Bandwidth control input (NBW pin); Initialization (INIT) input overrides NBW at power-up ◆ Dual reference clock inputs support LVDS, LVPECL, LVCMOS, LVTTL ◆ AutoSwitch (AUTO pin) - automatic (non-revertive) reference clock reselection upon clock failure; Hitless Switching (HS), Phase Build-out (PBO) options enable SONET (GR-253)/SDH (G.813) MTIE/TDEV compliance ◆ Acknowledge pin (REF_ACK pin) indicates the actively selected reference input ◆ Industrial temperature available ◆ Single 3.3V power supply ◆ Small 9 x 9 mm SMT (surface mount) package 28 29 30 31 32 33 34 35 36 M1040 (Top View) 18 17 16 15 14 13 12 11 10 P_SEL INIT nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND Figure 1: Pin Assignment Example I/O Clock Frequency Combinations Using M1040-11-155.5200 Input Reference Clock (MHz) 19.44 77.76 155.52 622.08 PLL Ratio (Pin Selectable) GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN 1 2 3 4 5 6 7 8 9 Output Clock (MHz) (Pin Selectable) 8 2 1 0.25 155.52 or 77.76 Table 1: Example I/O Clock Frequency Combinations * Specify VCSO center frequency at time of order. SIMPLIFIED BLOCK DIAGRAM Loop Filter M1040 NBW MUX PLL Phase Detector DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_ACK REF_SEL AUTO Auto INIT LOL MR_SEL2:0 3 Ref Sel 0 R Div VCSO 1 0 1 M Divider LOL Phase Detector M / R Divider P Divider (1 or 2) FOUT0 nFOUT0 FOUT1 nFOUT1 LUT P_SEL Figure 2: Simplified Block Diagram M1040 Datasheet Rev 0.1 M1040 VCSO Based Clock PLL with AutoSwitch Revised 11Nov2003 ● Integrated Circuit Systems, Inc. Communications Modules ● w w w. i c s t . c o m ● tel (508) 852-5400 Integrated Circuit Systems, Inc. M1040 VCSO BASED CLOCK PLL WITH AUTOSWITCH Preliminary Information PIN DESCRIPTIONS Number 1, 2, 3, 10, 14, 26 4 9 5 8 6 7 11, 19, 33 12 13 15 16 17 Name GND OP_IN nOP_IN nOP_OUT OP_OUT nVC VC VCC FOUT1 nFOUT1 FOUT0 nFOUT0 INIT I/O Configuration Description Ground Input Output Input Power Output Output Input No internal terminator No internal terminator Internal pull-UP resistor1 Internal pull-down1 Biased to Vcc/2 2 Input Internal pull-down resistor1 Input Internal pull-down resistor1 Biased to Vcc/2 3 Input Internal pull-down resistor1 Input Internal pull-down resistor1 Power supply ground connections. External loop filter connections. See Figure 5, External Loop Filter, on pg. 8. Power supply connection, connect to +3.3V. Clock output pair 1. Differential LVPECL. Clock output pair 0. Differential LVPECL. Power-on Initialization; LVCMOS/LVTTL: Logic 1 allows device to enter narrow mode if selected (in addition must have 8 LOL=0 counts) Logic 0 forced device into wide bandwidth mode. Post-PLL , P divider selection. LVCMOS/LVTTL. See Table 4, P Divider Selector Values and Frequencies, on pg. 3. Reference Differential LVPECL/ LVDS clock input Differential LVPECL/ LVDS, or single pair 1. ended LVCMOS/ LVTTL Reference clock input selection. LVCM...

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