Maker : ETC
Part No. : OZ962

  Datasheet PDF : OZ962.pdf
  Cross Reference : OZ962 Cross Reference
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Product Information

OZ962 High-Efficiency Inverter Controller FEATURES • • • • • • • • • Single-stage power conversion, input voltage range of 5V to 18V Reduces the number of components and board size by 30% compared with conventional design Supports both floating and grounded secondary designs 90% efficiency vs. typical 75% efficiency of conventional designs Internal open-lamp and short-circuit protections Wide dimming range Supports synchronization among multiple inverter modules Reliable 2 -winding transformer design, eliminates arcing problems Constant frequency, symmetrical, sinusoidal drive GENERAL DESCRIPTION The OZ962 is a unique high-efficiency, CCFL backlight controller. It generates symmetrical, near sinusoidal output voltage and current waveforms for driving a CCFL backlight. The OZ962 operates in a single, constant frequency, pulse-width-modulation (PWM) mode. Typical operating frequency ranges between 30 KHz to 100 KHz, depending on the CCFL and the transformer’s characteristics. Operating in a PWM push-pull manner, the transformer in the OZ962 backlight inverter requires only one primary winding and one secondary winding, with the secondary winding requiring no fold-back treatment. The OZ962 is available in both 16-pin SOIC and TSSOP packages. It is specified over the commercial temperature range: 0 oC to +70 oC. ORDERING INFORMATION OZ962R - 16 lead TSSOP OZ962G - 16-pin plastic SOP TYPICAL APPLICATION CIRCUIT VDD (+12V) ENA GND CN1 U1 16 REF VDD OZ962G 2 15 RT OVP 14 3 NC CT 4 13 SCP CLK 5 12 ADJ ENA 6 11 FB NDR 7 10 CMP PDR 8 9 GND SST 1 F1 1A Fast Fuse + C1 22u 25V R5 10K R10 100 3 C8 0.22u 4 5,6 7,8 R6 30 1.0K 2 Q1 1 U2 Q2 C6 2.2u 50V + R14 * 33T * 2200T C7 68p 3KV 3.5W R9 R1 220K 200K C9 .01u R2 10K C2 R3 5.1K 0.1u 330p C3 C5 220p R7 100K SI4559EY C4 0.1u R12 750 R11 1M R4 15K R8 0.5 R13 100 Figure 1. Typical Floating Secondary Application Circuit 03/01/00 ©Copyright 1999 by O2Micro OZ962-SF-2.7 All Rights Reserved Page 1 U.S. Patent #5,619,402 OZ962 FUNCTIONAL BLOCK DIAGRAM Ct(14) Rt(15) OVP(2) Under Voltage Lockout VDD(16) OSC RAMP OVP Voltage Generator OVP OVP=Vref-(Vdd - 1)(12.5/150) D=1.1(OVP)/2.5 - 0.2 NDR(11) Break Before Make N-Clamp Band Gap Reference REF(1) PDR(10) Vref (2.5V) OSC S RAMP Q Q P-Clamp R Error Amp. Vcmp 60k FB(6) 3V 1k CMP(7) Vdd 9k 30k SST 1/2F ADJ(5) 40k Ve Ve=Vcmp-2*(Vcmp-SST-Vgs) CLK(13) Dmax Clamp OVP 3µ A SST(9) 10µA SST OVP ENA(12) 2.0v 2µA ADJ SCP & OVP inhibited during start-up OVP SCP UVL shut down latch GND(8) SCP(4) Note: OVP – Over Voltage Protection SCP – Short-Circuit Protection UVL – Under Voltage Lockout Figure 2. Functional Block Diagram OZ962-SF-2.7 Page 2 OZ962 PIN DESCRIPTION Names REF OVP NC SCP ADJ FB CMP GND SST PDR NDR ENA CLK CT RT VDD Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I/O O I I I I O GND I O O I O I/O I/O PWR Description Reference voltage output. Nominal voltage is 2.5 V. Over-voltage protection setting. Refer to formula for OVP in block diagram on page 2 of this document. No connection. Short-circuit protection input. Reference voltage input for dimming control. Current sense feedback. Compensation for the current sense feedback. Ground. Tsst ~ 0.2 Csst (Vdd - 5), where Csst is the soft start capacitor value in µF and Tsst value is in µs. Gate drive output for the P-MOSFET. Gate drive output for the N-MOSFET. Enable input, active high (Vth is about 1.7 V). Open-drain clock output. Timing capacitor. CT and RT set the clock frequency. Timing resistor. Supply voltage input. ABSOLUTE MAXIMUM RATINGS VDD GND Logic inputs Power dissipation 18 V +/- 0.3 V -0.3 V to VDD+0.3 V 800 mW at 25 oC Operating temp. Operating junction temp. Storage temp. 0 oC to 70 oC 150 oC -55 to 150 oC RECOMMENDED OPERATING RANGE VDD Fosc Rosc 5V to 18V 30 KHz to 100 KHz 50 k to 150 k OZ962-SF-2.7 Page 3 OZ962 FUNCTIONAL SPECIFICATIONS Parameter Reference Voltage Nominal voltage Line regulation Load regulati...

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