Maker : Peregrine Semiconductor
Part No. : PE4259

  Datasheet PDF : PE4259.pdf
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Product Information

www.DataSheet4U.com Product Specification PE4259 Product Description The PE4259 UltraCMOS™ RF Switch is designed to cover a broad range of applications from near DC through 3000 MHz. This reflective switch integrates on-board CMOS control logic with a low voltage CMOS-compatible control interface, and can be controlled using either single-pin or complementary control inputs. Using a nominal +3-volt power supply voltage, a typical input 1 dB compression point of +33.5 dBm can be achieved. The PE4259 SPDT High Power UltraCMOS™ RF Switch is manufactured in Peregrine’s patented Ultra Thin Silicon (UTSi®) CMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. SPDT High Power UltraCMOS™ DC – 3.0 GHz RF Switch Features • Single-pin or complementary CMOS logic control inputs • Low insertion loss: 0.35 dB at 1000 MHz, 0.5 dB at 2000 MHz • Isolation of 30 dB at 1000 MHz, 20 dB at 2000 MHz • Typical input 1 dB compression point of +33.5 dBm • Ultra-small SC-70 package Figure 1. Functional Diagram Figure 2. Package Type SC-70 RFC 6-lead SC-70 RF1 RF2 CMOS Control Driver CTRL CTRL or VDD Table 1. Electrical Specifications @ +25 °C, VDD = 3 V (ZS = ZL = 50 Ω) Parameter Operation Frequency1 Insertion Loss Isolation Return Loss ‘ON’ Switching Time ‘OFF’ Switching Time Video Feedthrough 2 Conditions 1000 MHz 2000 MHz 1000 MHz 2000 MHz 1000 MHz 2000 MHz 50% CTRL to 0.1 dB of final value, 1 GHz 50% CTRL to 25 dB isolation, 1 GHz Minimum DC Typical 0.35 0.50 Maximum 3000 0.45 0.60 Units MHz dB dB dB dB dB dB us us mVpp dBm dBm 29 19 21 24 30 20 22 27 1.50 1.50 15 Input 1 dB Compression Input IP3 1000 MHz 1000 MHz, 20dBm input power 31.5 33.5 55 Notes: 1. Device linearity will begin to degrade below 10 MHz. 2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to High or High to Low in a 50 Ω test set-up, measured with 1ns risetime pulses and 500 MHz bandwidth. Document No. 70-0134-02 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 8 PE4259 Product Specification Figure 3. Pin Configuration (Top View) pin 1 Table 4. DC Electrical Specifications Parameter Min 2.3 Typ 3.0 9 Max 3.3 20 Units V µA V RF1 GND RF2 1 6 CTRL or VDD RFC CTRL VDD Power Supply Voltage IDD Power Supply Current (VDD = 3V, VCNTL = 3V) Control Voltage High Control Voltage Low 259 2 5 3 4 0.7x V DD 0.3x VDD V Table 2. Pin Descriptions Pin No. 1 2 3 4 5 Latch-Up Avoidance Description Pin Name RF1 GND RF2 CTRL RFC RF Port13 Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 3. Figure 4. Maximum Input Power Ground connection. Traces should be physically short and connected to ground plane for best performance. RF Port23 Switch control input, CMOS logic level. RF Common 3 This pin supports two interface options: Single-pin control mode. A nominal 3-volt supply connection is required. Complementary-pin control mode. A complementary CMOS control signal to CTRL is supplied to this pin. Bypassing on this pin is not required in this mode. 6 CTRL or VDD Table 3. Absolute Maximum Ratings Symbol VDD VI TST TOP PIN Parameter/Conditions Power supply voltage Voltage on any input Storage temperature range Operating temperature range Input power (50Ω) ESD Voltage (HBM, ML_STD 883 Method 3015.7) ESD Voltage (MM, JEDEC, JESD22-A114-B) Min -0.3 -0.3 -65 -40 Max 4.0 VDD+ 0.3 150 85 +344 2000 Units V V °C °C dBm V VESD 250 Notes: 3. All RF pins must be DC blocked with an external series capacitor or held at 0 VDC. 4. To maintain op...

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