Maker : Mitsubishi Electric Semiconductor
Part No. : PS22053

  Datasheet PDF : PS22053.pdf
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Product Information

MITSUBISHI SEMICONDUCTOR MITSUBISHI SEMICONDUCTOR PS22053 PS22053 TRANSFER-MOLD TYPE TRANSFER-MOLD TYPE INSULATED TYPE INSULATED TYPE PS22053 INTEGRATED POWER FUNCTIONS 1200V/10A low-loss 4th generation IGBT inverter bridge for 3 phase DC-to-AC power conversion www.DataSheet4U.com INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS • • • • For upper-leg IGBTS :Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection. For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC). Fault signaling : Corresponding to an SC fault (Lower-side IGBT) or a UV fault (Lower-side supply). Input interface : 5V line CMOS/TTL compatible (High active logic). APPLICATION AC400V 0.2kW~0.75kW inverter drive for small power motor control. Fig. 1 PACKAGE OUTLINES Dimensions in mm 30✕2.54(=76.2) 2.54±0.3 Heat sink side 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 48.6±0.6 22 23 24 25 26 27 28 18.5±0.5 2-φ4.5±0.2 8±0.3 10.16±0.3 67±0.3 79±0.5 16.1±0.3 20.4±0.5 QR Code A 42.6±0.5 Type name , Lot No. 44±0.5 8.2±0.5 (2.5) Heat sink side (2) Detail : A All external terminals are treated with lead free solder (ingredient : Sn-Cu) plating. (0.3) (1.7) (2) (0.3) 1. VUFS 2. VUFB 3. VP1 4. UP 5. VVFS 6. VVFB 7. VP1 8. VP 9. VWFS 10. VWFB 11. VP1 12. VPC 13. WP 14. VN1 15. VNC 16. CIN 17. CFO 18. FO 19. UN 20. VN 21. WN 22. P 23. U 24. V 25. W 26. NU 27. NV 28. NW 27.4±0.5 34±0.5 May 2005 MITSUBISHI SEMICONDUCTOR PS22053 TRANSFER-MOLD TYPE INSULATED TYPE Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE) CBW+ CBW– CBV+ CBV– CBU– CBU+ C1 : Tight tolerance, temp-compensated electrolytic type (Note : The capacitance depends on the PWM control scheme used in the applied system.) C2 : 0.22~2µF R-category ceramic capacitor for noise filtering High-side input (PWM) (5V line) (Note 1,2) Input signal Input signal Input signal conditioning conditioning conditioning Level shifter Level shifter Level shifter Protection circuit (UV) Protection circuit (UV) Protection circuit (UV) C2 C1 (Note 6) DIP-IPM www.DataSheet4U.com AC line input Inrush current limiter circuit P Drive circuit Drive circuit Drive circuit H-side IGBTS (Note 4) U V W M AC line output C Z (Note 8) N1 VNC NU NV NW L-side IGBTS CIN Drive circuit Z : ZNR (Surge absorber) C : AC filter (Ceramic capacitor 2.2~6.5nF) (Protection against common-mode noise) Input signal conditioning Fo logic Protection circuit Control supply Under-Voltage protection (UV) FO CFO Low-side input (PWM) (5V line) (Note 1, 2) Fault output (5V line) (Note 3, 5) (Note 7) VD VNC (15V line) Note1: 2: 3: 4: 5: 6: 7: 8: To prevent input signals oscillation, an RC coupling at each input terminal is recommended. By virtue of integrating HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer isolation is possible. Fo output is open drain type. The signal line should be pulled up to the positive side of a 5V supply with an approximate 10kΩ resistor. The wiring between the power DC-link capacitor and the P/N1 terminals should be as short as possible to protect DIP-IPM against catastrophic high surge voltage. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to mount closely to the P and N1 terminals. Fo output pulse width (t FO) should be determined by connecting external capacitor between CFO and VNC terminals. (Example : t FO=2.4ms(typ.) at CFO=22nF) High voltage (1200V or more) and fast recovery type (less than 100ns) diodes should be used for the bootstrap circuit. It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge dest...

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