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16/32-bit RISC microprocessorMaker : Samsung semiconductor
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2003.10.15 S3C2440X RISC MICROPROCESSOR PRODUCT OVERVIEW PRODUCT OVERVIEW INTRODUCTION This manual describes SAMSUNG's S3C2440X 16/32-bit RISC microprocessor. SAMSUNG’s S3C24440X is designed to provide hand-held devices and general applications with low-power, and high-performance microcontroller solution in small die size. To reduce total system cost, the S3C2440X includes the following components separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD Controller (STN & TFT), NAND Flash Boot Loader, System Manager (chip select logic and SDRAM Controller), 3-ch UART, 4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch Screen Interface, Camera interface, IIC-BUS Interface, IIS-BUS Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface, 2ch SPI and PLL for clock generation. The S3C2440X has been developed using an ARM920T core, 0.13um CMOS standard cells and a memory complier. Its low-power, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. It adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA). The S3C2440X offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length. By providing a complete set of common system peripherals, the S3C2440X minimizes overall system costs and eliminates the need to configure additional components. The integrated on-chip functions that are described in this document include: • • • • • • • • • • • • • • • 1.2V internal, 1.8V/2.5V/3.3V memory, 3.3V external I/O microprocessor with 16KB I-Cache/16KB DCache/MMU External memory controller (SDRAM Control and Chip Select logic) LCD controller (up to 4K color STN and 256K color TFT) with 1-ch LCD-dedicated DMA 4-ch DMAs with external request pins 3-ch UART (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO) / 2-ch SPI 1-ch multi-master IIC-BUS/1-ch IIS-BUS controller SD Host interface version 1.0 & Multi-Media Card Protocol version 2.11 compatible 2-port USB Host /1- port USB Device (ver 1.1) 4-ch PWM timers & 1-ch internal timer Watch Dog Timer 130-bit general purpose I/O ports / 24-ch external interrupt source Power control: Normal, Slow, Idle and Sleep mode 8-ch 10-bit ADC and Touch screen interface RTC with calendar function On-chip clock generator with PLL 1-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice. 2003.10.15 PRODUCT OVERVIEW S3C2440X FEATURES Architecture • • • • NAND Flash Boot Loader • • • • Integrated system for hand-held devices and general embedded applications. 16/32-Bit RISC architecture and powerful instruction set with ARM920T CPU core. Enhanced ARM architecture MMU to support WinCE, EPOC 32 and Linux. Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance. ARM920T CPU core supports the ARM debug architecture. Internal Advanced Microcontroller Bus Architecture (AMBA) (AMBA2.0, AHB/APB). Supports booting from NAND flash memory. 4KB internal buffer for booting. Supports storage memory for NAND flash memory after booting. Supports Advanced NAND flash Cache Memory • • • • 64-way set-associative cache with I-Cache (16KB) and D-Cache (16KB). 8words length per line with one valid bit and two dirty bits per line. Pseudo random or round robin replacement algorithm. Write-through or write-back cache operation to update the main memory. The write buffer can hold 16 words of data and four addresses. • • System Manager • â€... |
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