Maker : Texas Instruments
Part No. : SN74AUC1GU04

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SN74AUC1GU04 SINGLE INVERTER GATE www.ti.com SCES371L – SEPTEMBER 2001 – REVISED APRIL 2007 FEATURES • • Available in the Texas Instruments NanoFree™ Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Sub-1-V Operable Max tpd of 2.4 ns at 1.8 V Low Power Consumption, 10-µA Max ICC DBV PACKAGE (TOP VIEW) • • • • • • • ±8-mA Output Drive at 1.8 V Unbuffered Output Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DRY PACKAGE (TOP VIEW) YZP PACKAGE (BOTTOM VIEW) DCK PACKAGE (TOP VIEW) NC A GND 1 5 VCC NC A 1 2 3 5 VCC 2 GND 4 4 Y V WCC IE NC A 2 V5 E Y 3 4 GNDPR NC 1 6 GND A DNU 3 4 2 1 5 Y VCC 3 Y DNU - Do not use NC – No internal connection See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION This single inverter gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC1GU04 contains one inverter with an unbuffered output and performs the Boolean function Y = A. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. ORDERING INFORMATION TA PACKAGE (1) (2) NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) SON – DRY SOT (SOT-23) – DBV SOT (SC-70) – DCK (1) (2) (3) ORDERABLE PART NUMBER Reel of 3000 Reel of 5000 Reel of 300 Reel of 300 SN74AUC1GU04YZPR SN74AUC1GU04DRYR SN74AUC1GU04DBVR SN74AUC1GU04DCKR TOP-SIDE MARKING (3) _ _ _UD_ PREVIEW UU4_ UD_ –40°C to 85°C Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. DBV/DCK/DRY: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. www.DataSheet4U.com UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2007, Texas Instruments Incorporated SN74AUC1GU04 SINGLE INVERTER GATE SCES371L – SEPTEMBER 2001 – REVISED APRIL 2007 www.ti.com FUNCTION TABLE INPUT A H L OUTPUT Y L H LOGIC DIAGRAM (POSITIVE LOGIC) A 2 4 Y Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN VCC VI VO IIK IOK IO Supply voltage range Input voltage range (2) Output voltage range (2) VI < 0 VO < 0 Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND DBV package θJA Package thermal impedance (3) DCK package DRY package YZP package Tstg (1) (2) (3) Storage temperature range –65 –0.5 –0.5 –0.5 MAX 3.6 3.6 VCC + 0.5 –50 –50 ±20 ±100 206 252 234 132 150 °C °C/W UNIT V V V mA mA mA mA Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may...

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