Maker : Texas Instruments
Part No. : SN74AUC2G02

Datasheet PDF : SN74AUC2G02.pdf
Cross Reference : SN74AUC2G02 Cross Reference
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Product Information

SN74AUC2G02 DUAL 2-INPUT POSITIVE-NOR GATE www.ti.com SCES441C – MAY 2003 – REVISED JANUARY 2007 FEATURES • • Available in the Texas Instruments NanoFree™ Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial Power-Down-Mode Operation Sub-1-V Operable Max tpd of 1.8 ns at 1.8 V • • • • Low Power Consumption, 10 µA at 1.8 V ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) • • • DESCRIPTION/ORDERING INFORMATION This dual 2-input positive-NOR gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC2G02 performs the Boolean function Y = A + B or Y = A • B in positive logic. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA –40°C to 85°C PACKAGE (1) NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) SSOP – DCT VSSOP – DCU (1) (2) Reel of 3000 Reel of 3000 Reel of 3000 ORDERABLE PART NUMBER SN74AUC2G02YZPR SN74AUC2G02DCTR SN74AUC2G02DCUR TOP-SIDE MARKING (2) _ _ _UB_ U02_ U02_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. www.DataSheet4U.com PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2007, Texas Instruments Incorporated SN74AUC2G02 DUAL 2-INPUT POSITIVE-NOR GATE SCES441C – MAY 2003 – REVISED JANUARY 2007 www.ti.com FUNCTION TABLE (each gate) INPUTS A H X L B X H L OUTPUT Y L L H LOGIC DIAGRAM (POSITIVE LOGIC) 1 1A 1B 2A 2B 6 2 5 3 2Y 7 1Y Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN VCC VI VO VO IIK IOK IO Supply voltage range Input voltage range (2) Voltage range applied to any output in the high-impedance or power-off state (2) Output voltage range (2) Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND DCT package θJA Tstg (1) (2) (3) Package thermal impedance (3) Storage temperature range DCU package YZP package –65 VI < 0 VO < 0 –0.5 –0.5 –0.5 –0.5 MAX 3.6 3.6 3.6 VCC + 0.5 –50 –50 ±20 ±100 220 227 102 150 °C °C/W UNIT V V V V mA mA mA mA Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input a...

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