Maker : Texas Instruments
Part No. : SN74AUC2G08

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Product Information

SN74AUC2G08 DUAL 2-INPUT POSITIVE-AND GATE www.ti.com SCES477C – AUGUST 2003 – REVISED JANUARY 2007 FEATURES • • Available in the Texas Instruments NanoFree™ Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub-1-V Operable Max tpd of 1.5 ns at 1.8 V DCT PACKAGE (TOP VIEW) • • • • • • • Low Power Consumption, 10-µA at 1.8 V ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) YZP PACKAGE (BOTTOM VIEW) DCU PACKAGE (TOP VIEW) 1A 1B 2Y GND 1 2 3 4 8 7 6 5 VCC 1Y 2B 2A 1A 1B 2Y GND 1 2 3 4 8 7 6 5 VCC 1Y 2B 2A GND 2Y 1B 1A 4 5 3 6 2 7 1 8 2A 2B 1Y VCC See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION This dual 2-input positive-AND gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC2G08 performs the Boolean function A • B or Y = A + B in positive logic. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. For more information about AUC Little Logic devices, please refer to the TI application report, Applications of Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027. ORDERING INFORMATION TA PACKAGE (1) NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) –40°C to 85°C SSOP – DCT VSSOP – DCU (1) (2) Reel of 3000 Reel of 3000 Reel of 3000 ORDERABLE PART NUMBER SN74AUC2G08YZPR SN74AUC2G08DCTR SN74AUC2G08DCUR TOP-SIDE MARKING (2) _ _ _UE_ U08_ _ _ U08_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. www.DataSheet4U.com PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2007, Texas Instruments Incorporated SN74AUC2G08 DUAL 2-INPUT POSITIVE-AND GATE SCES477C – AUGUST 2003 – REVISED JANUARY 2007 www.ti.com FUNCTION TABLE (each gate) INPUTS CLK H L X D H X L OUTPUT Y H L L LOGIC DIAGRAM (POSITIVE LOGIC) 1A 1B 2A 2B 1 7 2 5 3 6 2Y 1Y Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN VCC VI VO VO IIK IOK IO Supply voltage range Input voltage range (2) Voltage range applied to any output in the high-impedance or power-off Output voltage range (2) Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND DCT package θJA Tstg (1) (2) (3) Package thermal impedance (3) Storage temperature range DCU package YZP package –65 VI < 0 VO < 0 state (2) –0.5 –0.5 –0.5 –0.5 MAX 3.6 3.6 3.6 VCC + 0.5 –50 –50 ±...

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