Maker : ATMEL Corporation
Part No. : T5744

Datasheet PDF : T5744.pdf
Cross Reference : T5744 Cross Reference
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Product Information

Features • Minimal External Circuitry Requirements, no RF Components on the PC Board Except • • • • • • • • • • • • Matching to the Receiver Antenna High Sensitivity, Especially at Low Data Rates SSO20 and SO20 package Fully Integrated VCO Supply Voltage 4.5 V to 5.5 V, Operating Temperature Range -40°C to 105°C Single-ended RF Input for Easy Adaptation to l/4 Antenna or Printed Antenna on PCB Low-cost Solution Due to High Integration Level Various Types of Protocols Supported (i.e., PWM, Manchester and Biphase) Distinguishes the Signal Strength of Several Transmitters via RSSI (Received Signal Strength Indicator) ESD Protection According to MIL-STD. 883 (4KV HBM) High Image Frequency Suppression Due to 1 MHz IF in Conjunction with a SAW Frontend Filter, up to 40 dB is thereby Achievable with Newer SAWs Power Management (Polling) is Possible by Means of a Separate Pin via the Microcontroller Receiving Bandwidth BIF = 600 kHz UHF ASK Receiver T5744 Description The T5744 is a PLL receiver device for the receiving range of f 0 = 300 MHz to 450 MHz. It is developed for the demands of RF low-cost data communication systems with low data rates and fits for most types of modulation schemes including Manchester, Biphase and most PWM protocols. Its main applications are in the areas of telemetering, security technology and keyless-entry systems. www.DataSheet4U.com Figure 1. System Block Diagram UHF ASK/FSK Remote control transmitter UHF ASK Remote control receiver 1 Li cell U2741B T5744 Demod. Data interface 1...3 µC Keys Encoder M44Cx9x XTO PLL IF Amp Antenna Antenna VCO PLL XTO Power amp. LNA VCO Rev. 4521B–RKE–01/03 1 Pin Configuration Figure 2. Pinning SO20 and SSO20 ENABLE LFGND MODE DATA DVCC RSSI XTO LFVCC n.c. 10 11 TEST 20 16 15 14 13 19 18 17 T5744 8 2 4 6 1 3 5 CDEM DGND AGND AVCC BR_0 BR_1 7 LNAGND Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol BR_0 BR_1 CDEM AVCC AGND DGND MIXVCC LNAGND LNA_IN n.c. LFVCC LF LFGND XTO DVCC MODE RSSI TEST ENABLE DATA Function Baud rate select LSB Baud rate select MSB Lower cut-off frequency data filter Analog power supply Analog ground Digital ground Power supply mixer High-frequency ground LNA and mixer RF input Not connected Power supply VCO Loop filter Ground VCO Crystal oscillator Digital power supply Selecting 433.92 MHz /315 MHz Low: 315 MHz (USA) High: 433.92 MHz (Europe) Output of the RSSI amplifier Test pin, during operation at GND Selecting operation mode Low: sleep mode High: receiving mode Data output 2 T5744 4521B–RKE–01/03 MIXVCC LNA_IN 9 12 LF T5744 Figure 3. Block Diagram BR_0 BR_1 CDEM ASKDemodulator and data filter RSSI Dem_out Data interface DATA RSSI AVCC RSSI IF Amp Test TEST AGND DGND 4. Order MODE DVCC ENABLE LFGND Standby logic LFVCC IF Amp MIXVCC LPF 3 MHz LNAGND LPF 3 MHz VCO XTO XTO f LNA_IN LNA 64 LF RF Front End The RF front end of the receiver is a heterodyne configuration that converts the input signal into a 1-MHz IF signal. According to Figure 3, the front end consists of an LNA (Low-Noise Amplifier), LO (Local Oscillator), a mixer and RF amplifier. The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal oscillator) generates the reference frequency fXTO. The VCO (Voltage-Controlled Oscillator) generates the drive voltage frequency fLO for the mixer. fLO is dependent on the voltage at Pin LF. fLO is divided by factor 64. The divided frequency is compared to fXTO by the phase frequency detector. The current output of the phase frequency detector is connected to a passive loop filter and thereby generates the control voltage VLF for the VCO. By means of that configuration, VLF is controlled in a way that fLO/64 is equal to fXTO. If fLO is determined, fXTO can be calculated using the following formula: fXTO = fLO/64 The XTO is a one-pin oscillator that operates at the series resonance of the...

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