Maker : Integrated Device Technology
Part No. : V103A

  Datasheet PDF : V103A.pdf
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Product Information

V103A TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO General Description The V103A LVDS display interface transmitter is primarily designed to support pixel data transmission between a video processing engine and a digital video display. The data rate supports up to SXGA+ resolutions and can be used in Plasma, Rear Projector, Front Projector, CRT and LCD display applications. It can also be used in other high-bandwidth parallel data applications and provides a low EMI interconnect over a low cost, low bus width cable up to several meters in length. The V103A converts 35 bits of CMOS/TTL data, clocked on the rising or falling edge of an input clock (selectable), into six LVDS (Low Voltage Differential Signaling) serial data stream pairs. In video applications the 35 bits is normally divided into 10 bits for each R, G and B channel and 5 control bits. When combined with the V104 LVDS display interface receiver, the V103A + V104 combination provides a 35-bit wide, 90 MHz transport. The rate of each LVDS channel is 630 Mbps for a 90MHz data input clock, 945 Mbps for 135MHz. Features • Pin compatible with THine THC63LVD103 • Wide pixel clock range: 8 - 135 MHz • Guaranteed operation over -20 to +85° C ambient temperature • Supports a wide range of video and graphics modes including VGA, SVGA, XGA, SXGA, SXGA+, NTSC, PAL, SDTV, and HDTV up to 1080I or 720P • Internal PLL requires no external loop filter • Selectable rising or falling clock edge for data alignment • Compatible with Spread Spectrum clock source • Reduced LVDS output voltage swing mode (selectable) to minimize EMI • CMOS/TTL data inputs can be configured for reduced input voltage swing • • • • Single 3.3 V supply Low power consumption CMOS design Power down mode 64-pin TQFP lead free package Block Diagram TA0-6 TB0-6 TC0-6 TD0-6 TE0-6 RS R/F /PWDN 7 7 7 7 7 TA+ TATB+ TBParallel to Serial TC+ TCTD+ TDTE+ TE- www.DataSheet4U.com CLKIN (8 to 135 MHz) PLL TCLK+ TCLK- V103A Datasheet 1 11/18/05 Revision 3.2 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 • t e l ( 4 0 8) 2 97 - 1 2 0 1 • w ww. i c s t . co m V103A TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO Pin Assignment TD4 TD3 TD2 TD1 R/F TD0 TC6 TC5 GND TC4 TC3 TC2 TC1 VCC TC0 TB6 TD5 GND TD6 TE0 TE1 TE2 VCC TE3 TE4 GND TE5 CLKIN /PWDN PLLGND PLLVCC TE6 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64-pin TQFP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TB5 GND TB4 TB3 TB2 RS TB1 TB0 TA6 GND TA5 TA4 TA3 TA2 TA1 TA0 www.DataSheet4U.com V103A Datasheet LVDSGND TE+ TETD+ TDTCLK+ TCLKTC+ TCLVDSGND LVDSVCC TB+ TBTA+ TALVDSGND 2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 11/18/05 Revision 3.2 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 • t e l ( 4 0 8) 2 97 - 1 2 0 1 • w ww. i c s t . co m V103A TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO Pin Descriptions Pin Number 30, 31 28, 29 24, 25 20, 21 18, 19 22, 23 33, 34, 35, 36, 37, 38, 40 41, 42, 44, 45, 46, 48, 49 50, 52, 53, 54, 55, 57, 58 59, 61, 62, 63, 64, 1, 3 4, 5, 6, 8, 9, 11, 16 13 43 60 51, 7 12 2, 10, 39, 47, 56 27 17, 26, 32 15 14 Pin Name TA+, TATB+, TBTC+, TCTD+, TDTE+, TETCLK+, TCLKTA0 ~ TA6 TB0 ~ TB6 TC0 ~ TC6 TD0 ~ TD6 TE0 ~ TE6 /PWDN RS R/F VCC CLKIN GND LVDSVCC LVDSGND PLLVCC PLLGND Pin Type Pin Description LVDS OUT LVDS Serial Data Output Pairs LVDS OUT LVDS Reference Clock Output Pair IN CMOS/TTL (or small signal) Data Bit Inputs IN IN IN Power IN Ground Power Ground Power Ground High: Normal device operation Low: Power down; all outputs become high impedance Voltage level on this pin sets LVDS output swing voltage and data input swing voltage; refer to the table at the bottom of this page. Input Clock triggering edge select. High: Rising edge; Low: Falling edge. Power supply pins for TTL inputs and digital circuitry. Clo...

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