Maker : Integrated Circuit Systems
Part No. : V104

  Datasheet PDF : V104.pdf
  Cross Reference : V104 Cross Reference
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Shortcut : V10-A500X  V10-H08X  V10-H14X  V10-H22X  V10-H30X  V1000LA160B  V1000LA80A  V10150C  V10150S  V103  V103A  V104  V10P10  V10P12  V10P45  V10P45S  V10PL45 

Product Information

V104 10 BIT LVDS RECEIVER FOR VIDEO General Description The V104 10 Bit LVDS Receiver for Video is designed to support video data transmission between display engines and video processing engines for television and projector applications. The V104 supports up to WXGA resolutions for Plasma, Rear Projection, Front Projection, CRT and LCD applications. The V104 converts the 6 LVDS (Low Voltage Differential Signaling) video data stream pairs to 35 www.DataSheet4U.com CMOS/TTL data bits with a rising or falling edge clock. The clock edge selection is performed using a dedicated pin. In conjunction with the V103 transmitter, the V104 can transmit 10 bits per color (R, G, B) along with 5 bits of control and timing data (HSYNC, VSYNC, DE, CNTL1, CNTL2) over a low EMI, low bus width connection including connectors and standard LVDS cabling. PRELIMINARY Features • • • • • • • • • Pin & function compatible with the THC63LVD104A Wide pixel clock range: 8 - 90 MHz Supports resolutions from 480p to WXGA Internal PLL does not require external loop filter Clock edge selection for TTL alignment selectable Power down mode Single 3.3V supply Low power consumption CMOS design 64-pin TQFP lead free package Block Diagram LVDS Input RA+/7 CMOS/TTL Output 7 RA6-RA0 RB6-RB0 RC6-RC0 RD6-RD0 RE6-RE0 CLKOUT RB+/RC+/RD+/RE+/RCLK+/(8 to 90 MHz) Serial to Parallel 7 7 7 PLL CMOS/TTL Input TEST PD OE R/F V104 Datasheet 1 1/12/05 Revision 1.6 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m V104 10 BIT LVDS RECEIVER FOR VIDEO PRELIMINARY Pin Assignment PVCC PGND RE+ RERD+ RDLGND RCLK+ RCLKRC+ RCLVCC RB+ RBRA+ RA64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 www.DataSheet4U.com Pin Descriptions Pin Number 50, 49 52, 51 55, 54 60, 59 62, 61 57, 56 40, 41, 42, 43, 45, 46, 47 32, 33, 34, 35, 36, 38, 39 22, 24, 25, 26, 27, 28, 29 14, 15, 17, 18, 19, 20, 21 Pin Name RA+, RARB+, RBRC+, RCRD+, RDRE+, RERCLK+, RCLKRA6 ~ RA0 RB6 ~ RB0 RC6 ~ RC0 RD6 ~ RD0 Pin Type LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN OUT OUT OUT OUT LVDS Data In LVDS Data In LVDS Data In LVDS Data In LVDS Data In LVDS Clock In CMOS/TTL Data Outputs CMOS/TTL Data Outputs CMOS/TTL Data Outputs CMOS/TTL Data Outputs V104 Datasheet RD4 RD3 RD2 RD1 RD0 RC6 VCC RC5 RC4 RC3 RC2 RC1 RC0 GND CLKOUT RB6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND TEST PD OE R/F RE6 RE5 RE4 VCC RE3 RE2 RE1 RE0 RD6 RD5 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64-pin TQFP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC RA0 RA1 RA2 GND RA3 RA4 RA5 RA6 RB0 RB1 VCC RB2 RB3 RB4 RB5 Pin Description 2 1/12/05 Revision 1.6 I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m V104 10 BIT LVDS RECEIVER FOR VIDEO Pin Number 6, 7, 8, 10, 11, 12, 13 2 3 4 5 www.DataSheet4U.com PRELIMINARY Pin Name RE6 ~ RE0 TEST PD OE R/F VCC CLKOUT GND LVCC LGND PVCC PGND Pin Type OUT IN IN IN IN Power OUT Ground Power Ground Power Ground CMOS/TTL Data Outputs. Not used. Tie LOW. Pin Description HIGH: normal operation; LOW: Power down (all outputs are “L”). HIGH: Output enable (normal operation); LOW: Output disable (all outputs are high impedance). Output Clock triggering edge select. High: Rising edge; Low: Falling edge. Power supply pins for TTL outputs and digital circuitry. Clock out. Ground pins for TTL outputs and digital circuitry. Power supply pins for LVDS inputs. Ground pins for LVDS inputs. Power supply pin for PLL circuitry. Ground pin for PLL circuitry. 9, 23, 37, 48 31 1, 16, 30, 44 53 58 64 63 PD 0 0 0 0 1 1 1 1 R/F 0 0 1 1 0 0 1 1 OE 0 1 0 1 0 1 0 1 Data Outputs (Rxn) High impedance All 0 High impedance All 0 High impedance Data Out High impedance Data Out CLKOUT High impedance Fixed Low High impedance Fixed Low High ...

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