Maker : ETC
Part No. : XE1201A

  Datasheet PDF : XE1201A.pdf
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XE1201A Data Sheet TLA RFA RFB DEMODULATOR SYMBOL SYN CHRO TLB FILTERING + IO OFFSET REDUCTION QO AVDD AGND DVDD DGND RXD CLKD SD BUS CONTROL POWER MANAGEMENT 90 DEG SC DE EN RF POWER AMP RFOU T DDS TXD RXTX VREF 90 DEG LO CLOCK TPA TPB RFGN D RFVDD TKA TKB TKC SWA SWB LOGND XTAL ;($  0+] /RZ3RZHU 8+) 7UDQVFHLYHU )HDWXUHV • • • • • • • YHU ORZSRZHU KDOIGXSOH[ RSHUDWLRQ GDWD UDWH XS WR  NELWV KLJK VHQVLWLYLW IHZ H[WHUQDO FRPSRQHQWV LQWHUQDO ELW VQFKURQL]HU ZLUH EXV IRU HDV PLFURFRQWUROOHU LQWHUIDFH • RXWSXW SRZHU SURJUDPPDEOH YLD EXV *HQHUDO 'HVFULSWLRQ 7KH ;($ LV D KDOIGXSOH[ )6. WUDQVFHLYHU IRU RSHUDWLRQ LQ WKH  0+] ,60 EDQG RSWLPL]HG DQG LQ WKH  0+] EDQG 7KH PRGXODWLRQ XVHG LV WKH &RQWLQXRXV 3KDVH  OHYHO )UHTXHQF 6KLIW .HLQJ &3)6. 7KH GLUHFW FRQYHUVLRQ ]HUR ,) UHFHLYHU DUFKLWHFWXUH HQDEOHV RQFKLS FKDQQHO ILOWHULQJ 7KH ;($ LQFOXGHV D ELW VQFKURQL]HU VR WKDW JOLWFK IUHH GDWD ZLWK VQFKURQL]HG FORFN FDQ GLUHFWO EH UHDG E D ORZ FRVW  ORZ FRPSOH[LW PLFUR FRQWUROOHU 7KH WUDQVPLWWHG SRZHU OHYHO FDQ DOVR EH FRQWUROOHG YLD WKH EXV 7KH ;($ PHHWV WKH , (76 VWDQGDUG DQG LV DYDLODEOH LQ D 74)3 SDFNDJH $SSOLFDWLRQV • • • • • • WHOHPHWU 5) VHFXULW VVWHPV ZLUHOHVV GDWD OLQN GRRU RSHQHUV UHPRWH FRQWURO ZLUHOHVV VHQVLQJ 4XLFN 5HIHUHQFH 'DWD Qvƒhpxhtr 2UGHULQJ ,QIRUPDWLRQ Qh…‡ Ur€ƒr…h‡ˆ…r …htr Y@ ! 6 #ǂÃ'$ Ã8 ° URAQ"! • • • • VXSSO YROWDJH 5) VHQVLWLYLW GDWD UDWH WUDQVPLWWHG SRZHU  9  G%P  NELWVV  G%P Cool Solutions XEMICS SA, Switzerland Tel: +41 32 720 51 70 Fax: +41 32 720 57 70 e-mail: info@xemics.com Web:www.xemics.com ;($  0+] /RZ3RZHU 8+) 7UDQVFHLYHU 'HWDLOHG 3LQ 'HVFULSWLRQ RFOUT RFA TLA RFVDD PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME EN DE AVDD TPA TPB AGND SC SD LOGND TKA TKB TKC SWA SWB RXTX VREF TXD CLKD RXD DGND XTAL XTAL DVDD QO IO RFA RFB RFGND RFOUT TLA TLB RFVDD DESCRIPTION EN RFGND RFB TLB IO QO DVDD XTAL XTAL DGND RXD CLKD TXD VREF Chip enable Bus data enable Supply voltage for analog Power amplifier tank circuit Power amplifier tank circuit Ground for analog Bus clock Bus data input Ground for local oscillator Oscillator tank circuit Oscillator tank circuit Oscillator tank circuit SAW resonator SAW resonator Receiver / transmitter enable Voltage stabilizer decoupling Data input stream Received data clock Received data output Ground for digital Reference oscillator Reference oscillator Supply voltage for digital Test pin Test pin RF input RF input Ground for RF Transmitter output Low noise amplifier tank circuit Low noise amplifier tank circuit Supply voltage for RF DE AVDD TPA TPB AGND SC LOGND SD RXTX SWA fig. 2: TQFP 32L package $EVROXWH 5DWLQJV • VXSSO YROWDJH  9 WR  9 • VWRUDJH WHPSHUDWXUH ƒ& WR ƒ& • RSHUDWLQJ WHPSHUDWXUH ƒ& WR ƒ& (OHFWULFDO &KDUDFWHULVWLFV Tamb = 25° C; VDD = 3.0 V; FLO = 433.92 MHz; +/- 125 kHz frequency deviation; 16 kbit/s pseudo random bit sequence unless otherwise specified  SWB TKA TKC TKB ;($  0+] /RZ3RZHU 8+) 7UDQVFHLYHU SYMBOL PARAMETER VDD IDDR IDDT Operating supply voltage Reception supply current Transmission supply current CONDITIONS Min 2.4 4.5 Typ 3.0 6 5.5 8 11 13.5 Max Units 5.5 7.5 V mA mA mA mA mA 65 1 500 - 15 dBm output power - 5 dBm output power + 2.5 dBm output power + 5 dBm output power Clock running Clock stopped 300 C13 = 0 ; C12 = 0 C13 = 0 ; C12 = 1 C13 = 1 ; C12 = 0 C13 = 1 ; C12 = 1 BER=1%, Rsource = 50Ω 8 kbit/s 16 kbit/s 64 kbit/s Parallel real part Parallel capacitive part Parallel capacitive part Funw =FLO ±125 kHz RFlevel = RFS+3dB Funw =FRF ±1MHz RFlevel = RFS+3dB 1 channel, BER=1% 3 dB cutoff frequency -40 < Tamb < +85° C 2.4 V < Vdd < 3.6 V -106 -104 -99 -12 39 0 250 programmable by 3-wire bus programmable by 3-wire bus +/-4 4 0 IDDS FR TP Standby current Freque...

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