Maker : Xemics
Part No. : XE88LC05A

  Datasheet PDF : XE88LC05A.pdf
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Product Information

Datasheet XE88LC05/05A Sensing Machine Data Acquisition MCU with Zooming ADC and DACs www.DataSheet4U.com XE88LC05/05A Sensing Machine Data Acquisition with 16+10 bit ZoomingADC™ and buffered 16 and 8 bit DACs General Description The XE88LC05A is a data acquisition ultra lowpower low-voltage system on a chip (SoC) with a high efficiency microcontroller unit embedded (MCU), allowing for 1 MIPS at 300uA and 2.4 V, and multiplying in one clock cycle. The XE88LC05A includes a high resolution acquisition path with the 16+10 bits ZoomingADC and two buffered DACs. The XE88LC05A is available with on chip ROM or Multiple-Time-Programmable (MTP) program memory. Key product Features • Low-power, high resolution ZoomingADC • • • • • 0.5 to 1000 gain with offset cancellation up to 16 bits analog to digital converter up to 13 inputs multiplexer 2 MIPS with 2.4 V to 5.5 V operation 300 µA at 1 MIPS over voltage range • • • • • • • Low-voltage low-power controller operation 22 kByte (8 kInstruction) MTP 520 Byte RAM data memory RC and crystal oscillators 5 reset, 22 interrupt, 8 event sources 8 bit and 16 bit buffered DACs 100 years MTP Flash retention at 55°C Applications • • • • • • • Portable, battery operated instruments Current loop powered instruments Wheatstone bridge interfaces Pressure and chemical sensors HVAC control Metering Sports watches, wrist instruments Ordering Information Product XE88LC05MI028* XE88LC05AMI000 XE88LC05AMI028 XE88LC05ARE000 XE88LC05ARE028 *Not for new designs Temperature range -40°C to 85 °C -40°C to 85 °C -40°C to 85 °C -40°C to 125 °C -40°C to 125 °C Memory type MTP MTP MTP ROM ROM Package LQFP64 die LQFP64 die LQFP64 Coo l Solu tion s f or Wir eles s Con nec ti vit y XEMICS SA • e-mail: info@xemics.com • web: www.xemics.com Datasheet XE88LC05/05A Sensing Machine Data Acquisition MCU with Zooming ADC and DACs TABLE OF CONTENTS Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Chapter 18 Chapter 19 Chapter 20 Chapter 21 Chapter 22 XE88LC05/LC05A Overview XE88LC05/LC05A Performance XE88LC05/LC05A CPU XE88LC05/LC05A Memory System Block Reset generator Clock generation Interrupt handler Event handler Low power RAM Port A Port B Port C Universal Asynchronous Receiver/Transmitter (UART) Universal Synchronous Receiver/Transmitter (USRT) Acquisition Chain (ZoomingADC™) Voltage multiplier Signal D/A (DAS) Bias D/A (DAB) Counters/Timers/PWM The Voltage Level Detector XE88LC05/LC05A Dimensions www.DataSheet4U.com D0304-40 Datasheet XE88LC05/05A 1. General overview CONTENTS 1.1 Top schematic General description 1.1.2 XE88LC05 vs XE88LC05A 1.2 Pin map 1.2.1 Bare die 1.2.2 LQFP-64 1.3 Pin assignment 1-2 1-2 1-4 1-4 1-4 1-5 1-6 www.DataSheet4U.com 1.1.1 1-1 LC05 - 1.2 – 24 avril 2003 D0304-40 Datasheet XE88LC05/05A 1.1 Top schematic 1.1.1 General description The top level block schematic of the circuit is shown in Figure 1-1. The heart of the circuit consists of the Coolrisc816® CPU core. This core includes an 8x8 multiplier and 16 internal registers. The bus controller generates all control signals for access to all data registers other than the CPU internal registers. www.DataSheet4U.com The reset block generates the adequate reset signals for the rest of the circuit as a function of the setup contained in its control registers. Possible reset sources are the power-on-reset (POR), the external pin RESET, the watchdog (WD), a bus error detected by the bus controller or a programmable pattern on Port A. Different low power modes are implemented. The clock generation and power management block sets up the clock signals and generates internal supplies for different blocks. The clock can be generated from the RC oscillator (this is the start-up condition), the crystal oscillator (XTAL) or an external clock source (...

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