Maker : Xemics
Part No. : XE88LC06A

  Datasheet PDF : XE88LC06A.pdf
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Data Sheet XE88LC06A www.DataSheet4U.com XE88LC06A Ultra Low-Power Low-Voltage Radio Machine General Description Applications • • • • • • RF companion chip RF system supervisor Portable, battery operated instruments Metering Remote control HVAC control The XE88LC06A is an ultra low-power low-voltage microcontroller based Radio Machine. It includes the revolutionary BitJockey, UART type of peripheral specialized for radio communication. XE88LC06A is available with on chip ROM or MultipleTime-Programmable (MTP) program memory. Key product Features • • • • • • • • • • • • Ultra low-power MCU, up to 7 MIPS 300 uA at 1 MIPS operation 6 uA at 32 kHz operation 1 uA time keeping Low-voltage operation (1.2 - 5.5 V supply voltage) 22 kB (8 kW) ROM/MTP, 512 B RAM 4 counters PWM, UART, BitJockey™ Analog matrix switching 4 low-power analog comparators independant RC and crystal oscillators 5 reset, 15 interrupt, 8 event sources Ordering Information Product XE88LC06AMI000 XE88LC06AMI014 XE88LC06AMI015 XE88LC06AMI026 XE88LC06ARI000 XE88LC06ARI014 XE88LC06ARI015 XE88LC06ARI026 Temperature range -40°C to 85 °C -40°C to 85 °C -40°C to 85 °C -40°C to 85 °C -40°C to 125°C -40°C to 125°C -40°C to 125°C -40°C to 125°C Memory type MTP MTP MTP MTP ROM ROM ROM ROM Package die SO24 SO28 TQFP32 die SO24 SO28 TQFP32 • 100 years MTP Flash retention at 55°C Cool Solutions for Wireless Connectivity XEMICS SA • e-mail: info@xemics.com • web: www.xemics.com Datasheet XE88LC06A TABLE OF CONTENTS Chapter 1. 2. 3. 4. 5. www.DataSheet4U.com 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. Title General overview XE88LC06A performance CPU Memory mapping Low power modes Reset generator Clock generation Interrupt handler Event handler Low power RAM Port A Port B Port D Radio Asynchronous Receiver/Transmitter (BitJockey™) Universal Asynchronous Receiver/Transmitter (UART) Universal Synchronous Receiver/Transmitter (USRT) Counters/PWM The Voltage Level Detector Low power comparators Dimensions D0303-136 Datasheet XE88LC06A 1. General overview 1.1 Top schematic 1-2 1-4 1-4 1-4 1-5 1-5 1-6 www.DataSheet4U.com 1.2 Pin map 1.2.1 TQFP-32 1.2.2 SO-28 1.2.3 SO-24 1.2.4 Bare die 1.3 Pin assignment 1-1 D0303-136 Datasheet XE88LC06A 1.1 Top schematic The top level block schematic of the circuit is shown in Figure 1-1. The heart of the circuit consists of the Coolrisc816 CPU (central processing unit) core. This core includes an 8x8 multiplier and 16 internal registers. The bus controller generates all control signals for access to all data registers other than the CPU internal registers. The reset block generates the adequate reset signals for the rest of the circuit as a function of the setup contained in its control registers. Possible reset sources are the power-on-reset (POR), the www.DataSheet4U.com external pin NRESET, the watchdog (WD), a bus error detected by the bus controller or a programmable pattern on Port A. The clock generation and power management block sets up the clock signals and generates internal supplies for different blocks. The clock can be generated from the RC oscillator (this is the start-up condition), the crystal oscillator (XTAL) or an external clock source (given on the XIN pin). The test controller generates all set-up signals for different test modes. In normal operation, it is used as a set of 8 low power RAM. If power consumption is important for the application, the variables that need to be accessed frequently should be stored in these registers rather than in the RAM. The IRQ handler routes the interrupt signals of the different peripherals to the IRQ inputs of the CPU core. It allows masking of the interrupt sources and it flags which interrupt source is active. Events are generally used to restart the processor after a HALT period without jumping to a specified address, i.e. the program execution resumes with the instruction following the HALT inst...

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